128Kx8 Bit High-Speed CMOS Static RAM(3.3V Operating).
Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Relax DC characteristics.
Item
I
CC
12ns
15ns
20ns
Draft Data
Aug. 5. 1998
Sep. 7. 1998
Previous
70mA
68mA
65mA
Changed
75mA
73mA
70mA
Mar. 3. 1999
Final
Remark
Preliminary
Preliminary
Rev. 2.0
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Changed Standby Current.
Item
Previous
Standby Current(Isb1)
0.3mA
2.3. Added Data Retention Characteristics.
Add 10ns part.
Changed
0.5mA
Rev. 3.0
Apr. 24. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 3.0
April 2000
PRELIMINARY
P
KM68V1002C/CL, KM68V1002CI/CLI
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM68V1002C/CL-10 : 80mA(Max.)
KM68V1002C/CL-12 : 75mA(Max.)
KM68V1002C/CL-15 : 73mA(Max.)
KM68V1002C/CL-20 : 70mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68V1002C/CLJ : 32-SOJ-400
KM68V1002C/CLT : 32-TSOP2-400CF
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
The KM68V1002C is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 131,072 words by 8 bits.
The KM68V1002C uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
KM68V1002C is packaged in a 400mil 32-pin plastic SOJ or
TSOP2 forward.
PIN CONFIGURATION
(Top View)
A
0
A
1
1
2
3
4
5
6
7
8
9
32 A
16
31 A
15
30 A
14
29 A
13
28 OE
27 I/O
8
26 I/O
7
ORDERING INFORMATION
KM68V1002C/CL-10/12/15/20
KM68V1002CI/CLI-10/12/15/20
Commercial Temp.
Industrial Temp.
A
2
A
3
CS
I/O
1
I/O
2
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
SOJ/
TSOP2
25 Vss
24 Vcc
23 I/O
6
22 I/O
5
21 A
12
20 A
11
19 A
10
18
17
A
9
A
8
I/O
3
10
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge Circuit
I/O
4
11
WE
A
4
A
5
12
13
14
15
16
Row Select
A
6
Memory Array
512 Rows
256x8 Columns
A
7
I/O
1
~I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
PIN FUNCTION
Pin Name
A
0
- A
16
WE
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
CS
OE
CS
WE
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
-2-
Revision 3.0
April 2000
PRELIMINARY
P
KM68V1002C/CL, KM68V1002CI/CLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
d
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.5**
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.5***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
10ns
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-ver.
Min
-2
-2
-
-
-
-
-
-
-
-
2.4
Max
2
2
80
75
73
70
30
5
0.5
0.4
-
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE
*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Revision 3.0
April 2000
PRELIMINARY
P
KM68V1002C/CL, KM68V1002CI/CLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
*
The a
bove test conditions are also applied at industrial temperature range.
Value
0V to 3V
3ns
1.5V
See below
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
319Ω
353
Ω
5pF*
* Capacitive Load consists of all components of the
京公网安备 11010802033920号
EEWORLD
