AMD-K6-III/450ACK datasheet, PDF

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AMD-K6-III/450ACK: DescriptionRISC Microprocessor, 32-Bit, 450MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，106 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AMD-K6-III/450ACK Overview

RISC Microprocessor, 32-Bit, 450MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321

AMD-K6-III/450ACK Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	PGA
package instruction	IPGA, SPGA321,37X37
Contacts	321
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	IC ALSO REQUIRES 3.135V-3.6V FOR I/O
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P321
JESD-609 code	e0
length	49.53 mm
low power mode	YES
Number of terminals	321
Maximum operating temperature	80 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Encapsulate equivalent code	SPGA321,37X37
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/3.3 V
Certification status	Not Qualified
Maximum seat height	3.63 mm
speed	450 MHz
Maximum supply voltage	2.1 V
Minimum supply voltage	1.9 V
Nominal supply voltage	2 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Preliminary Information

Mobile

AMD-K6-III-P

Processor

Data Sheet

Publication #

22655

Rev:

Issue Date:

September 1999

Amendment/0

Preliminary Information

22655C/0—September 1999

Mobile AMD-K6

-III-P Processor Data Sheet

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

About This Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii

Mobile AMD-K6

-III-P Processor . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

Super7™ Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Super7 Platform Enhancements: . . . . . . . . . . . . . . . . . . . . . . . . 3

Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Mobile AMD-K6

-III-P Processor Microarchitecture

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Enhanced RISC86

Microarchitecture . . . . . . . . . . . . . . . . . . . 6

Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . . 9

Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 11

Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Branch History Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3

2.4

2.5

2.6

2.7

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Mobile AMD-K6-III-P Processor Operation . . . . . . . . . . . . . . 35

5.1

5.2

Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Contents

iii

Preliminary Information

Mobile AMD-K6

-III-P Processor Data Sheet

22655C/0—September 1999

5.3

System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . 40

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SMM Operating Mode and Default Register Values . . . . . . . 40

SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

I/O Trap Dword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . . . 49

Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 51

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 51

Clock Switching Characteristics for 100-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Clock Switching Characteristics for 66-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . . 53

Output Delay Timings for 100-MHz Bus Operation . . . . . . . 54

Input Setup and Hold Timings for 100-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Output Delay Timings for 66-MHz Bus Operation . . . . . . . . 58

Input Setup and Hold Timings for 66-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . 62

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.1

7.2

7.3

7.4

7.5

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . 75

Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 76

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.1

Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . 77

Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 80

Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.1

321-Pin Staggered CPGA Package Specification . . . . . . . . . 81

Contents

AMD-K6-III/450ACK Related Products

	AMD-K6-III/450ACK	AMD-K6-III/400ACK	AMD-K6-III/433ACK	AMD-K6-III/366AFK	AMD-K6-III/380AFK	AMD-K6-III/350AFK
Description	RISC Microprocessor, 32-Bit, 450MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321	RISC Microprocessor, 32-Bit, 400MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321	RISC Microprocessor, 32-Bit, 433MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321	RISC Microprocessor, 32-Bit, 366MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321	RISC Microprocessor, 32-Bit, 380MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321	RISC Microprocessor, 32-Bit, 350MHz, CMOS, CPGA321, STAGGERED, CERAMIC, PGA-321
Parts packaging code	PGA	PGA	PGA	PGA	PGA	PGA
package instruction	IPGA, SPGA321,37X37	IPGA, SPGA321,37X37	IPGA, SPGA321,37X37	IPGA, SPGA321,37X37	IPGA, SPGA321,37X37	IPGA, SPGA321,37X37
Contacts	321	321	321	321	321	321
Reach Compliance Code	unknown	unknown	unknown	unknown	compliant	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Other features	IC ALSO REQUIRES 3.135V-3.6V FOR I/O	IC ALSO REQUIRES 3.135V-3.6V FOR I/O	IC ALSO REQUIRES 3.135V-3.6V FOR I/O	IC ALSO REQUIRES 3.135V-3.6V FOR I/O	IC ALSO REQUIRES 3.135V-3.6V FOR I/O	IC ALSO REQUIRES 3.135V-3.6V FOR I/O
Address bus width	32	32	32	32	32	32
bit size	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES
maximum clock frequency	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz
External data bus width	64	64	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CPGA-P321	S-CPGA-P321	S-CPGA-P321	S-CPGA-P321	S-CPGA-P321	S-CPGA-P321
length	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm
low power mode	YES	YES	YES	YES	YES	YES
Number of terminals	321	321	321	321	321	321
Maximum operating temperature	80 °C	80 °C	80 °C	80 °C	80 °C	80 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA	IPGA	IPGA	IPGA	IPGA	IPGA
Encapsulate equivalent code	SPGA321,37X37	SPGA321,37X37	SPGA321,37X37	SPGA321,37X37	SPGA321,37X37	SPGA321,37X37
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH
power supply	2/3.3 V	2/3.3 V	2/3.3 V	2.2,3.3 V	2.2,3.3 V	2.2,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.63 mm	3.63 mm	3.63 mm	3.63 mm	3.63 mm	3.63 mm
speed	450 MHz	400 MHz	433 MHz	366 MHz	380 MHz	350 MHz
Maximum supply voltage	2.1 V	2.1 V	2.1 V	2.3 V	2.3 V	2.3 V
Minimum supply voltage	1.9 V	1.9 V	1.9 V	2.1 V	2.1 V	2.1 V
Nominal supply voltage	2 V	2 V	2 V	2.2 V	2.2 V	2.2 V
surface mount	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	-	incompatible
JESD-609 code	e0	e0	e0	e0	-	e0
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
Base Number Matches	-	1	1	1	1	-

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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