White Electronic Designs
1GB – 2x64Mx64, SDRAM UNBUFFERED
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
Available with "WP" write protect on pin 81 option
• W3DG63126V-D2
3.3V ± 0.3V Power Supply
168 Pin DIMM JEDEC
• PCB: 30.50mm (1.20in)
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
W3DG64126V-D2
DESCRIPTION
The W3DG64126V is a 2x64Mx64 synchronous DRAM
module which consists of sixteen 64Mx8 SDRAM
components in TSOP II package and one 2K EEPROM
in an 8 Pin TSSOP package for Serial Presence Detect
which are mounted on a 168 Pin DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
*CBO
*CB1
Vss
NC
NC
V
CC
WE#
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0#
DNU
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
CC
V
CC
CK0
V
SS
DNU
CS2#
DQM2
DQM3
DNU
V
CC
NC
NC
*CB2
*CB3
V
SS
DQ16
DQ17
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
V
CC
DQ20
NC
*V
REF
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
***WP
**SDA
**SCL
V
CC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
*CB4
*CB5
V
SS
NC
NC
V
CC
CAS#
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1#
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
CC
CK1
A12
V
SS
CKE0
CS3#
DQM6
DQM7
*A13
V
CC
NC
NC
*CB6
*CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
CC
DQ52
NC
*V
REF
DNU
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
**SA0
**SA1
**SA2
V
CC
PIN NAMES
A0 – A12
BA0-1
DQ0-63
CK0-CK3
CKE0, CKE1
CS0# - CS3#
RAS#
CAS#
WE#
DQM0-7
V
CC
V
SS
SDA
SCL
DNU
NC
WP
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply
Ground
Serial data I/O
Serial clock
Do not use
No Connect
Write Protect
* These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
*** WP available on the W3DG63126V-D2 only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQM0
W3DG64126V-D2
DQM4
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS3#
CS2#
DQM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM6
DQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
A0 ~ A12, BA0 & 1
RAS#
CAS#
WE#
CKE0
SDRAM
SDRAM
SDRAM
SDRAM
8SDRAM
SCL
V
CC
WP
A0
SDA
A1
A2
WP
SA0 SA1 SA2
10K Ω
CKE1
DQn
V
CC
Vss
8SDRAM
SDRAM
10Ω
CK0/1/2/3
10Ω
Every DQpin of SDRAM
SDRAM
SDRAM
One 0.1uF Capacitors
per each SDRAM
To all SDRAMs
SDRAM
1.5pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
TSTG
PD
IOS
W3DG64126V-D2
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
8
50
Units
V
V
°C
W
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0°C
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
V
CC
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
—
-10
T
A
Typ
3.3
3.0
—
—
—
—
+70°C
Max
3.6
V
CCQ
+0.3
0.8
—
0.4
10
Unit
V
V
V
V
V
μA
1
2
I
OH
= -2mA
I
OL
= -2mA
3
Note
Note:
1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
CC
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V, V
REF
=1.4V
±
200mV
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0-CKE1)
Input Capacitance (CK0-CK3)
Input Capacitance (CS0#-CS3#)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
Max
66
66
66
16
21
15
66
15
Unit
pF
pF
pF
pF
pF
pF
pF
pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
I
DD
SPECIFICATIONS AND CONDITIONS
V
CC
, V
CCQ
= +3.3V ±0.3V; SDRAM component values only
MAX
PARAMETER/CONDITION
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; t
RC
= t
RC
(MIN)
STANDBY CURRENT: Power-Down Mode; All device devicebanks idle; CKE = LOW
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks
active after t
RCD
met; No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All
device banks active
AUTO REFRESH CURRENT
CKE = HIGH; CS# = HIGH
SELF REFRESH CURRENT: CKE < 0.2V
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
W3DG64126V-D2
SYMBOL
I
DD1
I
DD2
I
DD3
I
DD4
I
DD5
I
DD6
I
DD7
7
1,920
56
720
2,000
3,920
96
96
7.5
1,760
56
720
1,840
3,920
96
96
10
1,760
56
720
1,840
3,920
96
96
UNITS
mA
mA
mA
mA
mA
mA
mA
NOTES
1
1
2
t
RFC
= t
RFC
(MIN)
t
RFC
= 7.8125μs
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
V
CC
, V
CCQ
= +3.3V ±0.3V
AC CHARACTERISTICS
PARAMETER
Access timefrom CLK (pos.edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period
AUTOREFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
SYMBOL
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ(3)
t
HZ(2)
t
LZ
t
OH
t
OHN
t
RAS
t
RC
t
RCD
t
REF
t
RFC
t
RP
t
RRD
t
T
t
WR
1
2.7
1.8
37
60
15
64
66
15
14
0.3
1 CLK
+
7ns
14
Exit SELF REFRESH to ACTIVE command
t
XSR
67
1.2
120,000
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
0.8
1.5
5.4
5.4
1
2.7
1.8
44
66
20
64
66
20
15
0.3
1 CLK
+
7.5ns
15
75
1.2
120,000
MIN
7
MAX
5.4
5.4
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
5.4
6
1
2.7
1.8
50
66
20
64
66
20
15
0.3
MIN
7.5
MAX
5.4
6
1
2
3
3
8
10
1
2
1
2
1
2
MIN
W3DG64126V-D2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
10
MAX
6
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
ns
ns
ns
ns
ns
120,000
ns
ns
ns
ms
ns
ns
ns
1.2
ns
7
24
28
10
10
23
23
NOTE
27
1 CLK
+
7.5ns
15
80
ns
ns
25
20
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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