HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
2Gb NAND FLASH
HY27UF082G2A
HY27UF162G2A
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.4 / Mar. 2007
1
HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Document Title
2Gbit (256Mx8bit/128Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.01
0.1
0.2
Initial Draft.
1) Change NOP
2) Correct 5th Read ID
3) Chnage AC Timing Characteristics
1) Add x16 features.
1) Chnage AC Timing Characteristics
tR
Before
0.3
After
25
20
tCRRH
50
100
tRHOH
100
15
tRLOH
15
5
Nov. 21. 2006
Sep. 07. 2006
Preliminary
May. 18. 2006
Preliminary
History
Draft Date
Jan. 24. 2006
Remark
Preliminary
2) Add AC Timing Characteristics
- tCOH = 15ns (min)
3) Correct copy back function
4) Delet Preliminary.
0.4
1) Delete cache read function in x16 product
Mar. 21. 2007
Rev 0.4 / Mar. 2007
2
HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27UFxx2G2A
Memory Cell Array
= (2K+64) Bytes x 64 Pages x 2,048 Blocks
= (1K+32) Words x 64pages x 1,024 Blocks
CHIP ENABLE DON’T CARE
PAGE SIZE
- x8 device : (2K+64 spare) Bytes
: HY27UF082G2A
- x16 device : (1K+32 spare) Words
: HY27UF162G2A
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UF(08/16)2G2A-T(P)
: 48-pin TSOP1(12 x 20 x 1.2 mm)
-
HY27UF(08/16)2G2A-T (Lead)
-
HY27UF(08/16)2G2A-TP (Lead Free)
- HY27UF082G2A-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UF082G2A-UP (Lead Free)
SERIAL NUMBER OPTION
- Simple interface sith microcontroller
- 3rd cycle: Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle: Page size, Block size, Organization, Spare
size
- 5th cycle: Plane Number, Plane Size
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device : (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM
- Internal (2048+64) Byte buffer to improve the program
throughput
Rev 0.4 / Mar. 2007
3
HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The Hynix HY27UF(08/16)2G2A series is a 256Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided
into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command input. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Pro-
gram/Erase Controller automates all program and erase functions including pulse repetition, where required, and inter-
nal verification and margining of data.
The modify operations can be locked using the WP input pin or using the extended lock block feature described later.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UF(08/16)2G2A extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory. A cache read feature (x8) is also implemented. This feature allows to dramatically improve the read through-
put when consecutive pages have to be streamed out.
The HYNIX HY27UF(08/16)2G2A series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27UF082G2A
HY27UF162G2A
ORIZATION
x8
x16
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1 / 52-ULGA
48TSOP1
Rev 0.4 / Mar. 2007
4
HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Inputs / Outputs (x16 Only)
Data Inputs / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.4 / Mar. 2007
5
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