UPD421001C-70 datasheet, PDF - EEWORLD Datasheet

UPD421001C-70: DescriptionIC,DRAM,NIBBLE MODE,1MX1,CMOS,DIP,18PIN,PLASTIC; Categorystorage storage; File Size307KB，14 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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UPD421001C-70 Overview

IC,DRAM,NIBBLE MODE,1MX1,CMOS,DIP,18PIN,PLASTIC

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DIP
package instruction	DIP,
Contacts	18
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	NIBBLE
Maximum access time	70 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 code	R-PDIP-T18
memory density	1048576 bit
Memory IC Type	NIBBLE MODE DRAM
memory width	1
Number of functions	1
Number of ports	1
Number of terminals	18
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX1
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
refresh cycle	512
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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