Product Obsolete or Under Obsolescence
R
<
B
L
XC1700E, XC1700EL, and XC1700L
Series Configuration PROMs
Product Specification
DS027 (v3.5) June 25, 2008
8
Features
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
®
FPGAs
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration
Low-power CMOS floating-gate process
•
•
•
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
Available in compact plastic packages: 8-pin SOIC, 8-
pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-
pin PLCC or 44-pin VQFP
Programming support by leading programmer
manufacturers
Design support using the Xilinx Alliance and
Foundation™ software packages
Guaranteed 20 year life data retention
Lead-free (Pb-free) packaging available
•
•
•
•
•
•
•
•
•
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See
Figure 1
for a
simplified block diagram.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or
Foundation software compiles the FPGA design file into a
standard Hex format, which is then transferred to most
commercial PROM programmers.
X-Ref Target - Figure 1
VCC
VPP
GND
RESET/
OE
or
OE/
RESET
CE
CEO
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1:
Simplified Block Diagram (Does Not Show Programming Circuit)
© Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
1
R
Product Obsolete or Under Obsolescence
Configuration PROMs
XC1700E, XC1700EL, and XC1700L Series
Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
operation, this pin must be connected to V
CC
. Failure to do
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging. Do not
leave V
PP
floating!
V
CC
and GND
Positive supply and ground pins.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
PROM Pinouts
Pins not listed are "no connects."
"
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this
document describes the pin as RESET/OE, although the
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
Pin Name
8-pin
PDIP
(PD8/
PDG8)
SOIC
(SO8/
SOG8)
VOIC
(VO8/
VOG8)
1
2
3
4
5
6
7
8
20-pin
SOIC
(SO20)
20-pin
PLCC
(PC20/
PCG20)
44-pin
VQFP
(VQ44)
44-pin
PLCC
(PC44)
DATA
CLK
RESET/OE
(OE/RESET)
CE
GND
CEO
1
3
8
10
11
13
18
20
2
4
6
8
10
14
17
20
40
43
13
15
18, 41
21
35
38
2
5
19
21
24, 3
27
41
44
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I
CC
standby mode.
V
PP
V
CC
Capacity
Devices
XC1704L
XC1702L
XC1701/L
XC17512L
XC1736E
XC1765E/EL
XC17128E/EL
XC17256E/EL
CEO
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE and
OE inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO follows
CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset. Note that OE can be
programmed to be either active High or active Low.
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
36,288
65,536
131,072
262,144
V
PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
2
R
Product Obsolete or Under Obsolescence
Configuration PROMs
XC1700E, XC1700EL, and XC1700L Series
Pinout Diagrams
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
39
38
37
36
35
34
33
32
31
30
29
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPP
NC
6
5
4
3
2
1
44
43
42
41
40
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
7
8
9
10
11
12
13
14
15
16
17
44
43
42
41
40
39
38
37
36
35
34
VPP
NC
NC
NC
PC44
Top View
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO
NC
DS027_05_090602
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO
NC
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
DS027_07_090602
DATA(D0)
CLK
OE/RESET
CE
1
2
3
4
8
PD8/PDG8
7
VO8/VOG8
SO8/SOG8
6
VCC
VPP
CEO
GND
DS027_06_060705
Top View
5
SO20
Top
View
20
19
18
17
16
15
14
13
12
11
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
GND
DS027_08_110102
NC
GND
NC
NC
NC
9
10
11
12
13
CLK
NC
OE/RESET
NC
CE
18
4
5 PC20/PCG2017
6
Top View
16
15
7
14
8
3
2
1
20
19
NC
DATA(D0)
NC
VCC
NC
NC
VPP
NC
NC
CEO
DS027_09_060705
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
3
R
Product Obsolete or Under Obsolescence
Configuration PROMs
XC1700E, XC1700EL, and XC1700L Series
Xilinx FPGAs and Compatible PROMs
Device
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4002XL
XC4005XL
XC4010XL
XC4013XL/XLA
XC4020XL/XLA
XC4028XL/XLA
XC4028EX
XC4036EX/XL/XLA
XC4036EX
XC4044XL/XLA
XC4052XL/XLA
XC4062XL/XLA
XC4085XL/XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
XC5202
XC5204
XC5206
XC5210
XC5215
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
Configuration
Bits
53,984
95,008
119,840
147,552
178,144
247,968
329,312
422,176
61,100
151,960
283,424
393,632
521,880
668,184
668,184
832,528
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
42,416
70,704
106,288
165,488
237,744
559,200
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
PROM
XC17128E
(1)
XC17128E
XC17128E
XC17256E
XC17256E
XC17256E
XC1701
XC1701
XC17128EL
(1)
XC17256EL
XC17512L
XC17512L
XC17512L
XC1701L
XC1701
XC1701L
XC1701
XC1701L
XC1702L
XC1702L
XC1702L
XC1704L
XC1704L
XC1704L +
XC17512L
XC1704L+
XC1702L
XC1765E
XC17128E
XC17128E
XC17256E
XC17256E
XC1701L
XC1701L
XC1701L
XC1702L
XC1702L
XC1704L
XC1704L
XC1704L +
XC1701L
XC1704L +
XC1702L
1.
Device
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
Notes:
Configuration
Bits
630,048
863,840
1,442,016
1,875,648
2,693,440
3,340,400
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
PROM
XC1701L
XC1701L
XC1702L
XC1702L
XC1704L
XC1704L
XC1704L
2 of XC1704L
2 of XC1704L
2 of XC1704L
3 of XC1704L
4 of XC1704L
4 of XC1704L
The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Designers using the default slow configuration frequency (CCLK)
can use the XC1765E or XC1765EL for the noted FPGA devices.
Controlling PROMs
Connecting the FPGA device with the PROM:
•
•
•
•
The DATA output(s) of the of the PROM(s) drives the
D
IN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
CC
glitch.
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal power-
on-reset is always in step with the FPGA’s internal
power-on-reset. This may not be a safe assumption.
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D
IN
pin.
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
•
•
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
4
R
Product Obsolete or Under Obsolescence
Configuration PROMs
XC1700E, XC1700EL, and XC1700L Series
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (2
24
) and DONE goes High.
However, the FPGA configuration is then completely wrong,
with potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending on
the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration
program from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line. Synchronization
is provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial Mode provides a simple configuration interface.
Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially,
accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs provide additional memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See
Figure 2, page 6.
After configuration is complete, the address counters of
all cascaded PROMs are reset if the FPGA RESET pin
goes Low, assuming the PROM reset polarity option has
been inverted.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of D
IN
.
Programming the FPGA With Counters
Unchanged upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE pin is held Low, the address
counters are left unchanged after configuration is complete.
Therefore, to reprogram the FPGA with another program,
the DONE line is pulled Low and configuration begins at the
last value of the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Table 1:
Truth Table for XC1700 Control Inputs
Control Inputs
RESET
Inactive
Active
Inactive
Active
Notes:
1.
2.
3.
The XC1700 RESET input has programmable polarity.
TC = Terminal Count = highest address value. TC + 1 = address 0.
Pull DATA pin to GND or V
CC
to meet I
CCS
standby current.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
CE
Low
Low
High
High
Internal Address
If address < TC
(1)
: increment
If address > TC
(2)
: don’t change
Held reset
Not changing
Held reset
Outputs
DATA
Active
High-Z
High-Z
High-Z
(3)
High-Z
(3)
CEO
High
Low
High
High
High
I
CC
Active
Reduced
Active
Standby
Standby
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
5
Analogue and Mixed Signal
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