IS66WVD2M16ALL-7013BLI datasheet, PDF

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IS66WVD2M16ALL-7013BLI: DescriptionPseudo Static RAM, 2MX16, 70ns, CMOS, PBGA54, 6 X 8 MM, MO-207, VFBGA-54; Categorystorage storage; File Size948KB，52 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS66WVD2M16ALL-7013BLI Overview

Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA54, 6 X 8 MM, MO-207, VFBGA-54

IS66WVD2M16ALL-7013BLI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	DSBGA
package instruction	VFBGA, BGA54,6X9,30
Contacts	54
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	70 ns
Other features	IT ALSO OPERATES SYNCHRONOUS BURST MODE
I/O type	COMMON
JESD-30 code	R-PBGA-B54
JESD-609 code	e1
length	8 mm
memory density	33554432 bit
Memory IC Type	PSEUDO STATIC RAM
memory width	16
Number of functions	1
Number of terminals	54
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA54,6X9,30
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum standby current	0.00001 A
Maximum slew rate	0.045 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	6 mm

IS66WVD2M16ALL-7013BLI Preview

IS66WVD2M16ALL

Preliminary Information

32Mb Async and Burst CellularRAM 2.0

Overview

The IS66WVD2M16ALL is an integrated memory device containing 32Mbit Pseudo Static Random

Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device uses a

multiplexed address and data bus scheme to minimize pins and includes a industry standard burst

mode for increased read and write bandwidth. The device includes several power saving modes :

Reduced Array Refresh mode where data is retained in a portion of the array and Temperature

Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a

standard asynchronous mode and high performance burst mode. The die has separate power rails,

VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.

Features



Single device supports asynchronous and burst

operation



Mixed Mode supports asynchronous write and

synchronous read operation



Dual voltage rails for optional performance



VDD 1.7V~1.95V, VDDQ 1.7V~1.95V



Multiplexed address and data bus



ADQ0~ADQ15



Asynchronous mode read access : 70ns



Burst mode for Read and Write operation



4, 8, 16 or Continuous



Low Power Consumption



Asynchronous Operation < 25 mA



Burst operation < 45 mA (@133Mhz)



Standby < 110 uA(max.)



Deep power-down (DPD) < 3uA (Typ)



Low Power Feature



Reduced Array Refresh



Temperature Controlled Refresh



Operation Frequency up to 133MHz



Operating temperature Range

Industrial -40°C~85°C



Package: 54-ball VFBGA

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or

effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to

its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Rev.00B | March 2010

www.issi.com

- SRAM@issi.com

IS66WVD2M16ALL

Preliminary Information

General Description

CellularRAM™ (Trademark of MicronTechnology) products are high-speed, CMOS pseudo-static

random access memories developed for low-power, portable applications.

The 32Mb DRAM core device is organized as 2 Meg x 16 bits. This device is a variation

of the industry-standard Flash control interface, with a multiplexed address/data bus.

The multiplexed address and data functionality dramatically reduce the required

signal count, and increase READ/WRITE bandwidth.

To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a

transparent self-refresh mechanism. The hidden refresh requires no additional support

from the system memory controller and has no significant impact on device read/write

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices.

The refresh configuration register (RCR) is used to control how refresh is performed on

the DRAM array. These registers are automatically loaded with default settings during

power-up and can be updated anytime during normal operation.

Special attention has been focused on standby current consumption during self refresh.

CellularRAM products include three mechanisms to minimize standby current. Partial

array refresh (PAR) enables the system to limit refresh to only that part of the DRAM

array that contains essential data. Temperature-compensated refresh (TCR) uses an

on-chip sensor to adjust the refresh rate to match the device temperature — the refresh

rate decreases at lower temperatures to minimize current consumption during standby.

Deep power-down (DPD) enables the system to halt the refresh operation altogether

when no vital information is stored in the device. The system-configurable refresh

mechanisms are adjusted through the RCR.

This CellularRAM device is compliant with the industry-standard CellularRAM 2.0

feature set established by the CellularRAM Workgroup. It includes support for both

variable and fixed latency, with three drive strengths, a variety of wrap options, and a

device ID register (DIDR).

A16~A20

Address

Decode Logic

Refresh

Configuration Register

(RCR)

Device ID Register

(DIDR)

Bus

Configuration Register

(BCR)

2048K X 16

DRAM

Memory Array

Input

/Output

Mux

And

Buffers

CE#

WE#

OE#

CLK

ADV#

CRE

LB#

UB#

WAIT

Control

Logic

ADQ0~ADQ15

[ Functional Block Diagram]

www.issi.com

- SRAM@issi.com

Rev.00B | March 2010

IS66WVD2M16ALL

Preliminary Information

54Ball VFBGA Ball Assignment

LB#

ADQ8

ADQ9

VSSQ

VDDQ

ADQ14

ADQ15

A18

WAIT

OE#

UB#

ADQ10

ADQ11

ADQ12

ADQ13

A19

CLK

A17

ADV#

A16

CE#

ADQ1

ADQ3

ADQ4

ADQ5

WE#

CRE

ADQ0

ADQ2

VDD

VSS

ADQ6

ADQ7

A20

[Top View]

(Ball Down)

Rev.00B | March 2010

www.issi.com

- SRAM@issi.com

IS66WVD2M16ALL

Preliminary Information

Signal Descriptions

All signals for the device are listed below in Table 1.

Table 1. Signal Descriptions

Symbol

VDD

VDDQ

VSS

VSSQ

ADQ0~

ADQ15

A16~A20

LB#

UB#

CE#

OE#

WE#

CRE

ADV#

Type

Power Supply

Input / Output

Input

Description

Core Power supply (1.7V~1.95V)

I/O Power supply (1.7V~1.95V)

All VSS supply pins must be connected to Ground

All VSSQ supply pins must be connected to Ground

Address Input(A0~A15)

Data Input/Output (DQ0~DQ15)

Address Input(A16~A20)

Lower Byte select

Upper Byte select

Chip Enable/Select

Output Enable

Write Enable

Control Register Enable: When CRE is HIGH, READ and WRITE operations

access registers.

Address Valid signal

Signal that a valid address is present on the address bus. Address are

latched on the rising edge of ADV# during asynchronous Read/Write

operations. Addresses are latched on the rising edge of CLK with ADV#

low during synchronous operation.

Clock

Latches addresses and commands on the first rising CLK edge when

ADV# is active in synchronous mode. CLK must be kept static Low during

asynchronous Read/Write operations.

WAIT

Data valid signal during burst Read/Write operation. WAIT is used to

arbitrate collisions between refresh and Read/Write operation. WAIT is

also asserted at the end of a row unless wrapping within the burst length.

WAIT is asserted and should be ignored during asynchronous READ

operation. WAIT is gated by CE# and is high-Z when CE# is high.

CLK

Input

WAIT

Output

Rev.00B | March 2010

www.issi.com

- SRAM@issi.com

IS66WVD2M16ALL

Preliminary Information

Functional Description

All functions for the device are listed below in Table 2.

Table 2. Functional Descriptions

Mode

Power

CLK

ADV#

CE#

OE#

WE#

CRE

UB#/

LB#

WAIT

ADQ

[15:0]

Note

Asynchronous Mode

Read

Write

Standby

No Operation

Configuration

Deep Power-

Down

Active

Stand

Idle

Active

DPD

Low-Z

High-Z

Low-Z

High-Z

Low-Z

High-Z

Data-out

Data-in

High-Z

Config-Reg

Out

High-Z

6,7

5,7

Synchronous Mode (Burst Mode)

Async read

Async write

Standby

No operation

Initial

burst read

Initial

burst write

Burst

continue

Burst suspend

Configuration

Deep Power-

Down

Active

Stand

Idle

Active

DPD

Low-Z

High-Z

Low-Z

High-Z

Data-Out

Data-In

High-Z

Address

Data-In or

Data-Out

High-Z

Config-Reg

Out

High-Z

6,7

5,8

8,11

Rev.00B | March 2010

www.issi.com

- SRAM@issi.com

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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