Last updated 2/21/01
QuickNote #79
QL5064 Reference
Design using
Leonardo Spectrum
In this QuickNote we will go through the reference design for the QL5064.
The files needed for synthesis using Exemplar are the following.
•
PCI64.v or .vhd
•
Top_level.v (in this case called ql5064-1.v or .vhd)
•
And any other design files that are being used by the top-level file. For Verilog the
design files are (defines.v, add23p2.v, r64x32.v, ram64x32.v and macros.v). For
VHDL the design files are: (r64x32.vhd, ram64x32.vhd and macros.vhd)
All the necessary files are provided in the
ql5064ref_leo_v.zip
and
ql5064ref_leo_vhd.zip
files.
Note: The PCI64.v file that we are using is different from the one
provided in QuickWorks.
These files are for synthesis only, for simulation purposes the user will need the other
files that are under C:\pasic\design\reference\ql5064_rdk\
Therefore, the user should have two different directories, one for synthesis and one
for simulation.
In order to do synthesis in Leonardo Spectrum, we have the option of using the
Graphical User Interface method or by running a script.
For more documentation on using Leonardo Spectrum with Quicklogic, refer to
QuickNote 71, Leonardo Spectrum Help Files and User’s Guides and the
QuickWorks User’s Guide.
Using the script.
1. For this synthesis flow, there are two different .tcl scripts that are tailored to be
used in Leonardo Spectrum. There is one script for Verilog users and one for VHDL
users.
2. To use this script, invoke the ql5064-1.tcl by selecting File->Run Script from
Leonardo Exemplar.
3. The script will load the Verilog or VHDL files of the QL5064 reference design, then
elaborate and optimize it and write an EDIF netlist that SpDE can import to do place
and route.
4. This script is just an example. The user can modify the script to be used with
his/her own design that is targeting a QL5064 device.
5. In tcl, the '#' sign at the beginning of the line is to indicate a comment. The
provided scripts have comments on the portions that the user would need to modify
when targeting a QL5064 device.
Using the User Interface
If the user does not want to use the scripting method then he/she can use the user
interface method, which is a manual procedure. Here are the necessary steps:
1) Open Exemplar and select the Technology Tab, in order to select a device and
package.
As of this moment, the QL5064 device cannot be selected directly from the
Exemplar GUI, so we will have to select any pASIC3 device. As shown in Figure
1. Or, if using QuickWorks 9.0, select “none”, SpDE has the option to select
default parts when importing the EDIF file, (refer to #11).
Figure 1. Select Quicklogic device.
2) Now, select the “Input” tab. This is where we tell Exemplar to read and elaborate
the design. Here, select the working directory and then add the design files. In our
case, we only added the top-level file (ql5064ref1.v) because in our top-level file
we have used the `include directive to add the other design files.
3) Then, click on Read. This will read and elaborate the design.
Make
sure you do
not Run Pre-Optimization.
Figure 2. Read and Elaborate input files.
4) The next step is to set the constraints. To do this, you would need to select the
“Constraints” tab.
5) In this tab, at the bottom, you will be able to select the clock sub-tab. Then select
the clock signals in your design so that Leonardo inserts clock pads for them, as
shown in Figure 3.
Figure 3. Adding clock pads to the clk signal.