CY14B104L, CY14B104N
4 Mbit (512K x 8/256K x 16) nvSRAM
Features
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Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 512K bytes of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
20 ns, 25 ns, and 45 ns Access Times
Internally organized as 512K x 8 (CY14B104L) or 256K x 16
(CY14B104N)
Hands off Automatic STORE on power down with only a small
Capacitor
STORE to QuantumTrap
®
nonvolatile elements initiated by
software, device pin, or AutoStore
®
on power down
RECALL to SRAM initiated by software or power up
Infinite Read, Write, and Recall Cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20% to –10% operation
Commercial and Industrial Temperatures
48-ball FBGA and 44/54-pin TSOP II packages
Pb-free and RoHS compliance
Logic Block Diagram
[1, 2, 3]
Notes
1. Address A
0
- A
18
for x8 configuration and Address A
0
- A
17
for x16 configuration.
2. Data DQ
0
- DQ
7
for x8 configuration and Data DQ
0
- DQ
15
for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-07102 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 19, 2008
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CY14B104L, CY14B104N
Pinouts
Figure 1. Pin Diagram - 48 FBGA
48-FBGA
(x8)
48-FBGA
(x16)
Top View
(not to scale)
1
NC
NC
DQ
0
V
SS
V
CC
DQ
3
2
OE
NC
NC
DQ
1
DQ
2
NC
3
A
0
A
3
A
5
A
17
V
CAP
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
NC
DQ
5
DQ
6
NC
WE
A
11
6
NC
NC
DQ
4
V
CC
V
SS
DQ
7
NC
NC
[4]
Top View
(not to scale)
1
BLE
DQ
8
2
OE
BHE
3
A
0
A
3
A
5
A
17
V
CAP
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
DQ
1
DQ
3
DQ
4
DQ
5
WE
A
11
6
NC
DQ
0
DQ
2
V
CC
V
SS
DQ
6
DQ
7
[5]
NC
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
DQ
9
DQ
10
V
SS
DQ
11
V
CC
DQ
12
DQ
14
DQ
13
DQ
15
HSB
NC
[4]
[5]
HSB
NC
A
18
A
8
A
8
Figure 2. Pin Diagram - 44 Pin TSOP II
44-TSOP II
(x8)
44-TSOP II
(x16)
[6]
NC
[5]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x8)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[4]
NC
A
18
A
17
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x16)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
6. HSB pin is not available in 44-TSOP II (x16) package.
Document #: 001-07102 Rev. *L
Page 2 of 25
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CY14B104L, CY14B104N
Pinouts
(continued)
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
NC
[5]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
NC
[4]
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
54 - TSOP II
(x16)
Top View
(
not to scale)
Pin Definitions
Pin Name
A
0
– A
18
A
0
– A
17
DQ
0
– DQ
7
DQ
0
– DQ
15
WE
CE
OE
BHE
BLE
V
SS
V
CC
HSB
[6]
Input
Input
Input
Input
Input
Ground
IO Type
Input
Description
Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
Input/Output
Bidirectional Data IO Lines for x8 Configuration.
Used as input or output lines depending on
operation.
Bidirectional Data IO Lines for x16 Configuration.
Used as input or output lines depending on
operation.
Write Enable Input, Active LOW.
When selected LOW, data on the IO pins is written to the specific
address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE HIGH.
Byte High Enable, Active LOW.
Controls DQ
15
- DQ
8
.
Byte Low Enable, Active LOW.
Controls DQ
7
- DQ
0
.
Ground for the Device.
Must be connected to the ground of the system.
Power Supply
Power Supply Inputs to the Device.
Input/Output
Hardware Store Busy (HSB).
When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
will be driven HIGH for short time with standard output high current.
Power Supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect
No Connect.
This pin is not connected to the die.
Page 3 of 25
V
CAP
NC
Document #: 001-07102 Rev. *L
[+] Feedback
CY14B104L, CY14B104N
Device Operation
The CY14B104L/CY14B104N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104L/CY14B104N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the
“Truth Table For SRAM Operations”
on
page 15 for a complete description of read and write modes.
Figure 4
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to
DC Electrical
Characteristics
on page 7 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. A pull
up should be placed on WE to hold it inactive during power up.
This pull up is only effective if the WE signal is tri-state during
power up. Many MPU’s will tri-state their controls on power up.
This should be verified when using the pull up. When the
nvSRAM comes out of power-on-recall, the MPU must be active
or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
Vcc
SRAM Read
The CY14B104L/CY14B104N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
0-18
or A
0-17
determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF
10kOhm
Vcc
WE
V
CAP
V
SS
V
CAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins DQ
0–15
are written into the memory if the data is valid t
SD
before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16bit words. It is recommended that
OE be kept HIGH during the entire write cycle to avoid data bus
contention on common IO lines. If OE is left LOW, internal
circuitry turns off the output buffers t
HZWE
after WE goes LOW.
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB
[6]
pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104L/CY14B104N conditionally initiates a
STORE operation after t
DELAY
. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
When HSB is driven LOW by any means, SRAM read and write
operations that are in progress are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B104L/CY14B104N continues SRAM operations for
t
DELAY
.
During any STORE operation, regardless of how it is initiated,
the CY14B104L/CY14B104N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14B104L/CY14B104N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
AutoStore Operation
The CY14B104L/CY14B104N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB; Software Store activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104L/CY14B104N.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Document #: 001-07102 Rev. *L
Page 4 of 25
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CY14B104L, CY14B104N
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC
< V
SWITCH
), an internal RECALL request is latched. When
V
CC
again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B104L/CY14B104N
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence. Further, no read or write
operations must be done after the sixth address read for a
duration of soft-sequence processing time (t
SS
). If these condi-
tions are not met, the sequence is aborted and no STORE or
RECALL takes place.
To initiate the software STORE cycle, the following addresses
and read sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
CE
H
L
L
L
WE
X
H
L
H
OE, BHE, BLE
[3]
X
L
X
L
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. HSB will be driven LOW. It is important to use read
cycles and not write cycles in the sequence, although it is not
necessary that OE be LOW for a valid sequence. After the
t
STORE
cycle time is fulfilled, the SRAM is activated again for the
read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
A
15
- A
0
[7]
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
IO
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Power
Standby
Active
Active
Active
[8, 9]
Notes
7. While there are 19 address lines on the CY14B104L (18 address lines on the CY14B104N), only the 13 address lines (A
14
- A
2
) are used to control software modes.
The rest of the address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
9. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document #: 001-07102 Rev. *L
Page 5 of 25
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