1 k(T =with C;nF to = DV at=A+5; unless otherwise–5 V; V
BP/UP = +5 V; MODE = +5 V; A Source Resistance =
1
AGND
noted.)
A
DD
DD
SS
SS
IN
1
IN
REF
= +2.5 V; f
CLKIN
= 4.096 MHz;
Test Conditions/Comments
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity, T
MIN
to T
MAX
25°C
T
MIN
to T
MAX
Differential Nonlinearity, T
MIN
to T
MAX
Positive Full-Scale Error
3
Full-Scale Drift
4
Unipolar Offset Error
3
Unipolar Offset Drift
4
Bipolar Zero Error
3
Bipolar Zero Drift
4
Bipolar Negative Full-Scale Errors
3
Bipolar Negative Full-Scale Drift
4
Noise (Referred to Output)
DYNAMIC PERFORMANCE
Sampling Frequency, f
S
Output Update Rate, f
OUT
Filter Corner Frequency, f
–3 dB
Settling Time to ±0.0007% FS
SYSTEM CALIBRATION
Positive Full-Scale Calibration Range
Positive Full-Scale Overrange
Negative Full-Scale Overrange
Maximum Offset Calibration Ranges
5, 6
Unipolar Input Range
Bipolar Input Range
Input Span
7
ANALOG INPUT
Unipolar Input Range
Bipolar Input Range
Input Capacitance
Input Bias Current
1
LOGIC INPUTS
All Inputs Except CLKIN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
CLKIN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
I
IN
, Input Current
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
POWER REQUIREMENTS
Power Supply Voltages
Analog Positive Supply (AV
DD
)
Digital Positive Supply (DV
DD
)
Analog Negative Supply (AV
SS
)
Digital Negative Supply (DV
SS
)
Calibration Memory Retention
Power Supply Voltage
A/S Version
2
B Version
2
C Version
2
Unit
20
±0.0015
±0.003
±0.003
±0.5
±4
±16
±19/±37
±4
±16
±26
±67 +48/–400
±4
±16
±13
±34 +24/–200
±8
±32
±10/±20
1.6
f
CLKIN
/256
f
CLKIN
/1024
f
CLKIN
/409,600
507904/f
CLKIN
V
REF
+ 0.1
V
REF
+ 0.1
–(V
REF
+ 0.1)
–(V
REF
+ 0.1)
–0.4 V
REF
to +0.4 V
REF
0.8 V
REF
2 V
REF
+ 0.2
0 to 2.5
±2.5
20
1
20
±0.0007
±0.0015
±0.0015
±0.5
±4
±16
±19
±4
±16
±26
±67
±4
±16
±13
±34
±8
±32
±10
1.6
f
CLKIN
/256
f
CLKIN
/1024
f
CLKIN
/409,600
507904/f
CLKIN
V
REF
+ 0.1
V
REF
+ 0.1
–(V
REF
+ 0.1)
–(V
REF
+ 0.1)
–0.4 V
REF
to +0.4 V
REF
0.8 V
REF
2 V
REF
+ 0.2
0 to 2.5
±2.5
20
1
20
±0.0003
±0.0008
±0.0012
±0.5
±4
±16
±19
±4
±16
±26
±67
±4
±16
±13
±34
±8
±32
±10
1.6
f
CLKIN
/256
f
CLKIN
/1024
f
CLKIN
/409,600
507904/f
CLKIN
V
REF
+ 0.1
V
REF
+ 0.1
–(V
REF
+ 0.1)
–(V
REF
+ 0.1)
–0.4 V
REF
to +0.4 V
REF
0.8 V
REF
2 V
REF
+ 0.2
0 to 2.5
±2.5
20
1
Bits
% FSR typ
% FSR max
% FSR max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
LSB max
LSB typ
LSB rms typ
Hz
Hz
Hz
sec
V max
V max
V max
V max
V max
V min
V max
V
V
pF typ
nA typ
Guaranteed No Missing Codes
Temp Range: 0°C to +70°C
Specified Temp Range
Temp Range: 0°C to +70°C
Specified Temp Range
For Full-Scale Input Step
System calibration applies to
unipolar and bipolar ranges.
After calibration, if A
IN
> V
REF
,
the device will output all 1s.
If A
IN
< 0 (unipolar) or –V
REF
(bipolar), the device will
output all 0s.
0.8
2.0
0.8
3.5
10
0.4
DV
DD
– 1
±10
9
0.8
2.0
0.8
3.5
10
0.4
DV
DD
– 1
±10
9
0.8
2.0
0.8
3.5
10
0.4
DV
DD
– 1
±10
9
V max
V min
V max
V min
µA max
V max
V min
µA max
pF typ
I
SINK
= 1.6 mA
I
SOURCE
= 100 µA
4.5/5.5
4.5/AV
DD
–4.5/–5.5
–4.5/–5.5
2.0
4.5/5.5
4.5/AV
DD
–4.5/–5.5
–4.5/–5.5
2.0
4.5/5.5
4.5/AV
DD
–4.5/–5.5
–4.5/–5.5
2.0
V min/V max For Specified Performance
V min/V max
V min/V max
V min/V max
V min
–2–
REV. E
AD7703
Parameter
POWER REQUIREMENTS
DC Power Supply Currents
8
Analog Positive Supply (AI
DD
)
Digital Positive Supply (DI
DD
)
Analog Negative Supply (AI
SS
)
Digital Negative Supply (DI
SS
)
Power Supply Rejection
9
Positive Supplies
Negative Supplies
Power Dissipation
Normal Operation
Standby Operations
10
A, B, C
S
A/S Version
2
B Version
2
C Version
2
Unit
Test Conditions/Comments
2.7
2
2.7
0.1
70
75
37
2.7
2
2.7
0.1
70
75
37
2.7
2
2.7
0.1
70
75
37
mA max
mA max
mA max
mA max
dB typ
dB typ
mW max
µW
max
µW
max
Typically 2 mA
Typically 1 mA
Typically 2 mA
Typically 0.03 mA
20
40
20
40
20
40
SLEEP
= Logic 1,
Typically 25 mW
SLEEP
= Logic 0,
Typically 10
µW
NOTES
1
The A
IN
pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the A
IN
pin to AGND is necessary.
Source resistance should be 750 or less.
2
Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3
Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
4
Total drift over the specified temperature range after calibration at power-up at 25
°C.
This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
5
In Unipolar mode, the offset can have a negative value (–V
REF
) such that the Unipolar mode can mimic Bipolar mode operation.
6
The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7
For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale
points. When using less than the maximum input span, the span range may be placed anywhere within the range of
±
(V
REF
+ 0.1).
8
All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9
Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10
CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
DV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DV
DD
to AV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Analog Input Voltage to AGND . . . AV
SS
– 0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . .
±
10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model
AD7703AN
AD7703BN
AD7703CN
AD7703AR
AD7703BR
AD7703CR
AD7703AQ
AD7703BQ
AD7703CQ
AD7703SQ
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Linearity
Error
(% FSR)
0.003
0.0015
0.0012
0.003
0.0015
0.0012
0.003
0.0015
0.0012
0.003
Package
Options*
N-20
N-20
N-20
R-20
R-20
R-20
Q-20
Q-20
Q-20
Q-20
*N
= Plastic DIP; R = SOIC; Q = CERDIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E
–3–
AD7703
TIMING CHARACTERISTICS
Parameter
f
CLKIN3, 4
Limit at T
MIN
, T
MAX
(A, B Versions)
200
5
200
5
50
50
0
50
1000
3/f
CLKIN
100
250
300
790
l/f
CLKIN
+ 200
4/f
CLKIN
+ 200
5
35
160
160
150
250
200
1, 2
(AV
DD
= DV
DD
= +5 V
10%; AV
SS
= DV
SS
= –5 V 10%; AGND = DGND = O V;
f
CLKIN
= 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
DD
; unless otherwise noted.)
Conditions/Comments
Master Clock Frequency: Internal Gate Oscillator
Typically 4.096 MHz
Master Clock Frequency: Externally Supplied
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time
SC1, SC2 Hold Time after CAL Goes High
SLEEP High to CLKIN High Setup Time
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/f
CLKIN
+ 100 ns typ)
CS High to Hi-Z Delay
Serial Clock Input Frequency
SCLK Input High Pulsewidth
SCLK Low Pulsewidth
Data Access Time (CS Low to Data Valid). Typically 80 ns.
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS High to Hi-Z Delay
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
Limit at T
MIN
, T
MAX
(S, T Versions)
Unit
200
5
200
5
50
50
0
50
1000
3/f
CLKIN
100
250
300
790
l/f
CLKIN
+ 200
4/f
CLKIN
+ 200
5
35
160
160
150
250
200
kHz min
MHz max
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
MHz max
ns min
ns min
ns max
ns max
ns max
ns max
t
r5
t
f 5
t
1
t
2
t
3 6
SSC MODE
t
4 7
t
5
t
6
7
t
8
t
98
t
108, 9
SEC MODE
f
SCLK
t
11
t
12
t
137, 10
t
1411
t
158
t
168
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4
The AD7703 is production tested with f
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7
t
4
and t
13
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t
9
, t
10
, t
15
, and t
16
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9
If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
CAL
I
OL
1.6mA
t
1
SC1, SC2
t
2
SC1, SC2 VALID
TO
OUTPUT
PIN
+ 2.1V
C
L
IOH
Figure 2. Calibration Control Timing
200 A
100pF
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
CLKIN
t
3
SLEEP
Figure 3. Sleep Mode Timing
–4–
REV. E
AD7703
CS
CS
t
10
SDATA
DATA
VALID
HI-Z
t
15
SDATA
DATA
VALID
HI-Z
Figure 4. SSC Mode Data Hold Time
CLKIN
DRDY
CS
Figure 5b. SEC Mode Data Hold Time
CS
t
7
t
12
t
11
SCLK
HI-Z
t
8
t
9
t
8
t
5
HI-Z
SCLK
t
4
t
13
t
14
DB19
DB18
DB1
t
16
DB0
HI-Z
SDATA
HI-Z
SDATA
HI-Z
DB19
DB18
DB1
DB0
HI-Z
Figure 5a. SEC Mode Timing Diagram
Figure 6. SSC Mode Timing Diagram
DEFINITION OF TERMS
Linearity Error
Positive Full-Scale Overrange
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero-scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full-scale, a point
1.5 LSB above the last code transition (111 . . . 110 to 111 . . .
111). The error is expressed as a percentage of full scale.
Differential Linearity Error
Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +V
REF
(for example, noise
peaks or excess voltages due to system gain errors in system
calibration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter.
Negative Full-Scale Overrange
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSB. A differential linearity specification of
±
1 LSB or less
guarantees monotonicity.
Positive Full-Scale Error
This is the amount of overhead available to handle voltages below
–V
REF
without overloading the analog modulator or overflowing
the digital filter. Note that the analog input will accept negative
voltage peaks even in the Unipolar mode.
Offset Calibration Range
Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (V
REF
±
3/2 LSB).
It applies to both positive and negative analog input ranges and
is expressed in microvolts.
Unipolar Offset Error
In the system calibration modes (SC2 low), the AD7703 calibrates
its offset with respect to the A
IN
pin. The offset calibration range
specification defines the range of voltages, expressed as a
percentage of V
REF
, that the AD7703 can accept and still accurately
calibrate offset.
Full-Scale Calibration Range
This is the range of voltages that the AD7703 can accept in the
system calibration mode and still correctly calibrate full scale.
Input Span
Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the
Unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating
in the Bipolar mode. It is expressed in microvolts.
Bipolar Negative Full-Scale Error
In system calibration schemes, two voltages applied in sequence
to the AD7703’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7703 can accept
and still accurately calibrate gain. The input span is expressed
as a percentage of V
REF.
This is the deviation of the first code transition from the ideal
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