a
FEATURES
Throughput:
570 kSPS (Warp Mode)
500 kSPS (Normal Mode)
444 kSPS (Impulse Mode)
INL: 2.5 LSB Max ( 0.0038% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 45 kHz
THD: –100 dB Typ @ 45 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI
®
/QSPI
TM
/MICROWIRE
TM
/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
115 mW Maximum,
21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP)
48-Lead Chip Scale Package (LFCSP)
Pin-to-Pin Compatible Upgrade of the AD7660
APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
GENERAL DESCRIPTION
16-Bit, 570 kSPS
PulSAR
®
Unipolar CMOS ADC
AD7664
*
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND
DVDD
DGND
OVDD
SERIAL
PORT
SWITCHED
CAP DAC
16
D[15:0]
BUSY
PARALLEL
INTERFACE
CLOCK
PD
RESET
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RD
CS
SER/PAR
OB/2C
OGND
AD7664
IN
INGND
WARP
IMPULSE
CNVST
Table I. PulSAR Selection
Type/kSPS
Pseudo
Differential
True Bipolar
True
Differential
18-Bit
Simultaneous/
Multichannel
100–250
500–570
800–1000
AD7651
AD7650/AD7652 AD7653
AD7660/AD7661 AD7664/AD7666 AD7667
AD7663
AD7675
AD7678
AD7665
AD7676
AD7679
AD7654
AD7655
AD7671
AD7677
AD7674
The AD7664 is a 16-bit, 570 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains a high speed 16-bit sampling ADC,
an internal conversion clock, error correction circuits, and both
serial and parallel system interface ports.
The AD7664 is hardware factory-calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It features a very high sampling rate mode (Warp), a fast mode
(Normal) for asynchronous conversion rate applications, and for
low power applications, a reduced power mode (Impulse) where
the power is scaled with the throughput.
It is fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process, with correspondingly low cost and is available in a
48-lead LQFP and a tiny 48-lead LFCSP with operation specified
from –40°C to +85°C.
PRODUCT HIGHLIGHTS
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
1. Fast Throughput
The AD7664 is a 570 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL
The AD7664 has a maximum integral nonlinearity of 2.5 LSBs
with no missing 16-bit code.
3. Single-Supply Operation
The AD7664 operates from a single 5 V supply and dissipates
only a maximum of 115 mW. In Impulse Mode, its power
dissipation decreases with the throughput to, for instance, only
21
µW
at a 100 SPS throughput. It consumes 7
µW
maximum
when in power-down.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7664 –SPECIFICATIONS
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
Full-Scale Error
2
Unipolar Zero Error
2
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
REFERENCE
External Reference Voltage Range
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
V
OL
V
OH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
4
AVDD
DVDD
5
OVDD
5
Power Dissipation
5
Conditions
Min
16
V
IN
– V
INGND
V
IN
V
INGND
f
IN
= 10 kHz
570 kSPS Throughput
0
–0.1
–0.1
62
7
See Analog Input Section
1.75
570
1
2
500
2.25
444
+2.5
+1.5
0.7
REF = 2.5 V
AVDD = 5 V
±
5%
f
IN
= 100 kHz
f
IN
= 45 kHz
f
IN
= 100 kHz
f
IN
= 45 kHz
f
IN
= 100 kHz
f
IN
= 45 kHz
f
IN
= 100 kHz
–60 dB Input, f
IN
= 100 kHz
±
5
±
3
90
100
100
–100
–100
90
89
30
18
2
5
Full-Scale Step
2.3
570 kSPS Throughput
2.5
115
250
AVDD – 1.85
±
0.08
±
15
V
REF
+3
+0.5
Typ
Max
Unit
Bits
V
V
V
dB
µA
µs
kSPS
ms
µs
kSPS
µs
kSPS
LSB
1
LSB
Bits
LSB
% of FSR
LSB
LSB
dB
3
dB
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
ns
V
µA
V
V
µA
µA
In Warp Mode
In Warp Mode
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
1
0
0
–2.5
–1
16
–0.3
2.0
–1
–1
+0.8
OVDD + 0.3
+1
+1
Parallel or Serial 16-Bits
Conversion Results Available
Immediately after
Completed Conversion
0.4
I
SINK
= 1.6 mA
I
SOURCE
= –500
µA
OVDD – 0.6
V
V
4.75
4.75
2.7
500 kSPS Throughput
5
5
15.5
3.8
100
5.25
5.25
5.25
V
V
V
mA
mA
µA
mW
µW
µW
500 kSPS Throughput
4
100 SPS Throughput
6
In Power-Down Mode
7
115
21
7
–2–
REV. E
AD7664
Parameter
TEMPERATURE RANGE
8
Specified Performance
Conditions
T
MIN
to T
MAX
Min
–40
Typ
Max
+85
Unit
°C
NOTES
1
LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15
µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In Normal Mode.
5
Tested in Parallel Reading Mode.
6
In Impulse Mode.
7
With all digital inputs forced to OVDD or OGND, respect
ively.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
REFER TO FIGURES 11 AND 12
Convert Pulse Width
Time between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
2
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH (INVSCLK Low)
3
Internal SCLK LOW (INVSCLK Low)
3
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
2
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
5
1.75/2/2.25
Typ
Max
Unit
ns
µs
ns
µs
ns
ns
µs
ns
ns
Note 1
25
1.5/1.75/2
2
10
1.5/1.75/2
250
10
1.5/1.75/2
45
5
40
15
10
10
10
25/275/525
4
40
30
9.5
4.5
3
3
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
75
10
10
10
2.75/3/3.25
1/1.25/1.5
50
5
3
5
5
25
10
10
16
NOTES
1
In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
REV. E
–3–
AD7664
ABSOLUTE MAXIMUM RATINGS
1
IN
2
, REF, INGND, REFGND to AGND
. . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . .
±
0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . .
±
7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
Digital Inputs
Except the Databus D(7:4) . . . . . –0.3 V to DVDD + 3.0 V
Databus D(7:4) . . . . . . . . . . . . . . –0.3 V to OVDD + 3.0 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for the device in free air:
48-Lead LQFP;
θ
JA
= 91°C/W,
θ
JC
= 30°C/W.
4
Specification is for device in free air:
48-Lead LFCSP;
θ
JA
= 26°C/W.
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
500 A
I
OH
*IN
SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
ORDERING GUIDE
Model
AD7664AST
AD7664ASTRL
AD7664ACP
AD7664ACPRL
EVAL-AD7664CB
1
EVAL-CONTROL-BRD2
2
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale (LFCSP)
Chip Scale (LFCSP)
Evaluation Board
Controller Board
Package Option
ST-48
ST-48
CP-48
CP-48
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL-BRD2 for evaluation/
demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7664 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. E
AD7664
PIN CONFIGURATION
REFGND
REF
36
AGND
35
CNVST
34
PD
33
RESET
32
CS
31
RD
30
DGND
29
BUSY
28
D15
27
D14
26
D13
25
D12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
AGND
1
AVDD
2
NC
3
DGND
4
OB/2C
5
WARP
6
IMPULSE
7
SER/PAR
8
D0
9
D1
10
D2
11
D3
12
NC = NO CONNECT
PIN 1
IDENTIFIER
AD7664
TOP VIEW
(Not to Scale)
D7/RDC/SDIN
OGND
DVDD
DGND
D8/SDOUT
OVDD
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D9/SCLK
D10/SYNC
INGND
NC
NC
NC
NC
NC
IN
NC
NC
NC
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3, 40–42,
44–48
4
5
Mnemonic
AGND
AVDD
NC
DGND
OB/2C
Type
P
P
Description
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
Must Be Tied to the Ground Where DVDD Is Referred.
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a twos complement output from
its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/PAR.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state
of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Mode.
DI
DI
6
WARP
DI
7
8
9–12
13
IMPULSE
SER/PAR
D[0:3]
D4
or EXT/INT
DI
DI
DO
DI/O
14
D5
or INVSYNC
DI/O
15
D6
or INVSCLK
DI/O
REV. E
–5–
D11/RDERROR
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