HY57V168010CLTC-8 datasheet, PDF

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HY57V168010CLTC-8: DescriptionSynchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 X 0.725 INCH, 0.80 MM PITCH, TSOP2-44; Categorystorage storage; File Size118KB，11 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V168010CLTC-8 Overview

Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 X 0.725 INCH, 0.80 MM PITCH, TSOP2-44

HY57V168010CLTC-8 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	44
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G44
JESD-609 code	e6
length	18.41 mm
memory density	16777216 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	44
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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HY57V168010C

2 Banks x 1M X 8 Bit Synchronous DRAM

DESCRIPTION

The Hyundai HY57V168010C is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory

applications which require large memory density and high bandwidth. HY57V168010C is organized as 2banks of

1,048,576x8.

HY57V168010C is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-

width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or

write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3V

0.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 44pin TSOP-II with 0.8mm

of pin pitch

All inputs and outputs referenced to positive edge of

system clock

Data mask function by DQM

Internal two banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 1, 2, 3 Clocks

ORDERING INFORMATION

Part No.

HY57V168010CLTC-8

HY57V168010CLTC-10P

HY57V168010CLTC-10S

HY57V168010CLTC-10

Clock Frequency

125MHz

100MHz

Organization

Interface

Package

2Banks x 1Mbits x 8

100MHz

LVTTL

400mil

44pin TSOP II

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied

Rev. 1.5/Dec.98

HY57V168010CLTC-8 Related Products

	HY57V168010CLTC-8	HY57V168010CLTC-10S	HY57V168010CLTC-10	HY57V168010CLTC-10P
Description	Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 X 0.725 INCH, 0.80 MM PITCH, TSOP2-44	Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 X 0.725 INCH, 0.80 MM PITCH, TSOP2-44	Synchronous DRAM, 2MX8, 8ns, CMOS, PDSO44, 0.400 X 0.725 INCH, 0.80 MM PITCH, TSOP2-44	Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 X 0.725 INCH, 0.80 MM PITCH, TSOP2-44
Maker	SK Hynix	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,	TSOP2,
Contacts	44	44	44	44
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	6 ns	6 ns	8 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G44	R-PDSO-G44	R-PDSO-G44	R-PDSO-G44
JESD-609 code	e6	e6	e6	e6
length	18.41 mm	18.41 mm	18.41 mm	18.41 mm
memory density	16777216 bit	16777216 bit	16777216 bit	16777216 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	8	8	8	8
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	44	44	44	44
word count	2097152 words	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000	2000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	2MX8	2MX8	2MX8	2MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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