N80C286 datasheet, PDF - EEWORLD Datasheet

N80C286: DescriptionMicroprocessor, 16-Bit, 12.5MHz, CMOS, PQCC68, PLASTIC, LCC-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，59 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric Compare View All

N80C286 Overview

Microprocessor, 16-Bit, 12.5MHz, CMOS, PQCC68, PLASTIC, LCC-68

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	unknown
Address bus width	24
bit size	16
boundary scan	NO
maximum clock frequency	12.5 MHz
External data bus width	16
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
length	24.2 mm
low power mode	YES
Number of terminals	68
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.83 mm
speed	12.5 MHz
Maximum slew rate	125 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	24.2 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

	N80C286	A80C286
Description	Microprocessor, 16-Bit, 12.5MHz, CMOS, PQCC68, PLASTIC, LCC-68	Microprocessor, 16-Bit, 12.5MHz, CMOS, CPGA68, PGA-68
Is it Rohs certified?	incompatible	incompatible
Maker	Intel	Intel
Parts packaging code	LCC	PGA
package instruction	QCCJ, LDCC68,1.0SQ	PGA, PGA68,11X11
Contacts	68	68
Reach Compliance Code	unknown	compliant
Address bus width	24	24
bit size	16	16
boundary scan	NO	NO
maximum clock frequency	12.5 MHz	12.5 MHz
External data bus width	16	16
Format	FIXED POINT	FIXED POINT
Integrated cache	NO	NO
JESD-30 code	S-PQCC-J68	S-CPGA-P68
JESD-609 code	e0	e0
length	24.2 mm	29.46 mm
low power mode	YES	YES
Number of terminals	68	68
Maximum operating temperature	85 °C	85 °C
Package body material	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCJ	PGA
Encapsulate equivalent code	LDCC68,1.0SQ	PGA68,11X11
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.83 mm	4.57 mm
speed	12.5 MHz	12.5 MHz
Maximum slew rate	125 mA	125 mA
Maximum supply voltage	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	PIN/PEG
Terminal pitch	1.27 mm	2.54 mm
Terminal location	QUAD	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	24.2 mm	29.46 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components