DATASHEET
ISL6353
Multiphase PWM Regulator for VR12 DDR Memory Systems
The ISL6353 is a three-phase PWM buck regulator controller for
VR12 DDR memory applications. The multi-phase
implementation results in better system performance, superior
thermal management, lower component cost and smaller PCB
area.
The ISL6353 has two integrated power MOSFET drivers for
implementing a cost effective and space saving power
management solution.
The PWM modulator of the ISL6353 is based on Intersil’s Robust
Ripple Regulator™ (R
3
) technology. Compared with the
traditional multi-phase buck regulator, the R
3
modulator
commands variable PWM switching frequency during load
transients, achieving faster transient response. R
3
also naturally
goes into pulse frequency modulation operation in light load
conditions to achieve higher light load efficiency.
The ISL6353 is designed to be completely compliant with VR12
specifications. The ISL6353 has a serial VID (SVID) bus
communicating with the CPU. The output can be programmed for
1-, 2- or 3-phase interleaved operation. The output voltage and
power state can also be controlled independent of the serial VID
bus.
The ISL6353 has several other key features. It supports DCR
current sensing with a single NTC thermistor for DCR
temperature compensation or accurate resistor current
sensing. It also has remote voltage sense, adjustable switching
frequency, current monitor, OC/OV protection and power-good.
Temperature monitor and thermal alert is available too.
FN6897
Rev 0.00
September 15, 2011
Features
• VR12 Serial Communications Bus
• Precision Voltage Regulation
- 5mV Steps with VID Fast/Slow Slew Rates
• Supports Two Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Programmable 1, 2 or 3-Phase Operation
• Adaptive Body Diode Conduction Time Reduction
• Superior Noise Immunity and Transient Response
• Pin Programmable Output Voltage and Power State Mode
• Output Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable Switching Frequency
• Resistor Programmable VBOOT, Power State Operation,
SVID Address Setting, I
MAX
• Excellent Dynamic Current Balance Between Phases
• OCP/WOC, OVP, OT Alert, PGOOD
• Small Footprint 40 Ld 5x5 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
• DDR Memory
95
COMP
200mV/DIV
94
93
EFFICIENCY (%)
92
91
90
89
88
87
1.5V PS1 2ph CCM
1.5V PS0
1.5V PS2 1ph DE
1.35VPS0
1.35V PS1 2ph CCM
1.35VPS2 1ph DE
VDDQ = 1.5V
50mV/DIV
PHASE1/2/3
5V/DIV
26A STEP LOAD
1V/DIV
20µs/DIV
86
85
0
10
20
30
40
50
LOAD (A)
60
70
80
FIGURE 1. FAST TRANSIENT RESPONSE
FIGURE 2. ISL6353EVAL1Z EFFICIENCY vs LOAD
FN6897 Rev 0.00
September 15, 2011
Page 1 of 30
ISL6353
Simplified Application Circuit Using Inductor DCR Current Sensing
+5V
DUAL
VIN
+5V
DUAL
VR_ON
VDDP
VDD
VIN
VIN (5VSB/12V DUAL)
ADDR
PROG2
PROG1
RNTC
°C
µP
{
NTC
SDA
ALERT#
SCLK
VW
COMP
FB
BOOT1
UG1
PH1
LG1
GND
+12V
PH1
VO1
BOOT2
UG2
PH2
ISL6353
LG2
GND
+5V
+12V
VCTRL
VCC
ISL6596
BOOT
UGATE
PHASE
GND
LGATE
PH3
VO3
PH2
VO2
VDDQ
VCCSENSE
VSSSENSE
PH1
PH2
PH3
VSEN
RTN
FB2
ISEN1
ISEN2
ISEN3
DRIVER
PWM3
VSET1
PWM
VO1
VO2
VO3
°C
VSUMN
ISUMN
VSET2
PSI
GND PAD
VR_HOT#
PGOOD
ISUMP
IMON
PH1
PH2
PH3
FN6897 Rev 0.00
September 15, 2011
OVP
Page 2 of 30
ISL6353
Block Diagram
VR_ON
PSI
VREADY
PROG
SDA
ALERT#
SCLK
VSET1
VSET2
ADDR
IMAX
VBOOT
TMAX
DROOP
# OF PHASES FOR PS1
SET (A/D)
D/A
DIGITAL
INTERFACE
DAC
IBAL
PHASE CURRENT
BALANCE
A/D
T_MONITOR
IMON
ISEN1
ISEN2
ISEN3
PROG
VIN
BOOT2
POWER-ON RESET
(POR)
VDD
PROG1
PROG2
NTC
VR_HOT#
T_MONITOR
TEMP MONITOR
DRIVER
UG2
PH2
VW
DAC
+
RTN
FB2
FB
-
+
?
+
GND
E/A
R
3
MODULATOR
PWM3
DRIVER
LG2
COMP
DRIVER
BOOT1
UG1
DROOP
PH1
VDDP
ISUMP
+
-
CURRENT
SENSE
OC AND WOC
PROTECTION
DRIVER
LG1
ISUMN
GND
IMON
OV PROTECTION
PGOOD
VSEN
OVP
FN6897 Rev 0.00
September 15, 2011
Page 3 of 30
ISL6353
Pin Configuration
VSET1
ISL6353
(40 LD TQFN)
TOP VIEW
PROG2
BOOT2
VSET2
ADDR
GND
31
30 LG2
29 VDDP
28 PWM3
27 LG1
GND
(BOTTOM PAD)
26 GND
25 PH1
24 UG1
23 BOOT1
22 PROG1
21 VIN
11
FB
12
FB2
13
ISEN3
14
ISEN2
15
ISEN1
16
VSEN
17
RTN
18
ISUMN
19
ISUMP
20
VDD
OVP
UG2
33
PH2
32
40
SDA
ALERT#
SCLK
VR_ON
PGOOD
IMON
VR_HOT#
NTC
VW
1
2
3
4
5
6
7
8
9
39
38
37
PSI
36
35
34
COMP 10
Pin Descriptions
PIN NUMBER
1, 2, 3
4
5
6
SYMBOL
DESCRIPTION
SDA, ALERT#, SCLK Serial communication bus signals connected between the CPU and the voltage regulator.
VR_ON
PGOOD
IMON
Voltage regulator enable input. A high level logic signal on this pin enables the VR.
Open-drain output to indicate the regulator is ready to supply regulated voltage. Use an appropriate external pull-up
resistor.
Output current monitor pin. IMON sources a current proportional to the regulator output current. A resistor
connected from this pin to ground will set a voltage that is proportional to the load current. This voltage is sampled
with an internal ADC to produce a digital IMON signal that can be read through the serial communications bus.
Thermal overload output indicator.
Thermistor input to the VR_HOT# circuit.
Window voltage set pin used to set the switching frequency. A resistor from this pin to COMP programs the
switching frequency (18k gives approximately 300kHz).
This pin is the output of the error amplifier.
This pin is the inverting input of the error amplifier.
This pin switches in an RC network from VOUT to FB in PS1 and PS2 modes to help improve transient performance
and phase margin when dropping phases in low power states. There is a switch between the FB2 pin and the FB
pin. The switch is off in the PS0 state and on in the PS1 and PS2 states. If this function is not needed, the pin can
be left open.
Individual current sensing input for Phase 3. Leave this pin open when ISL6353 is configured in 2-phase mode.
Individual current sensing input for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2,
and the controller will run in 1-phase mode.
Individual current sensing input for Phase 1.
Output voltage sense pin. Connect to the output voltage (typically VDDQ) at the desired remote voltage sensing
location.
7
8
9
10
11
12
VR_HOT#
NTC
VW
COMP
FB
FB2
13
14
15
16
ISEN3
ISEN2
ISEN1
VSEN
FN6897 Rev 0.00
September 15, 2011
Page 4 of 30
ISL6353
Pin Descriptions
(Continued)
PIN NUMBER
17
18, 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SYMBOL
RTN
ISUMN and ISUMP
VDD
VIN
PROG1
BOOT1
UG1
PH1
GND
LG1
PWM3
VDDP
LG2
GND
PH2
UG2
BOOT2
PROG2
PSI
DESCRIPTION
Output voltage sense return pin. Connect to the ground at desired remote sensing location.
Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP.
5V bias power.
Input supply voltage, used for input supply feed-forward compensation.
The program pin for the voltage regulator I
MAX
setting. Refer to Table 6.
Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT1 pin.
Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side
MOSFET.
Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1.
This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side
MOSFET.
PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other
phases to operate.
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF using an
MLCC capacitor to the ground plane close to the IC.
Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side
MOSFET.
This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side
MOSFET.
Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT2 pin.
The program pin for the voltage regulator V
BOOT
voltage, droop enable/disable and the number of active phases
for PS1 mode.
This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to
ground, the controller will refer only to the power state indicated by the serial communication bus register. If the
pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high,
the controller will enter the PS2 state.
This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator
with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to
the VID setting indicated by the serial communication bus register.
This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator
with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the
VID setting indicated by the serial communication bus register.
An inverter output, latched high for an overvoltage event. It is reset by POR.
This pin sets the address offset register, range from 0 to 13 (0h to Dh).
Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground
pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground
planes in PCB internal layers.
37
VSET2
38
VSET1
39
40
-
OVP
ADDR
GND (Bottom Pad)
FN6897 Rev 0.00
September 15, 2011
Page 5 of 30
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