xr
JANUARY 2005
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.1
GENERAL DESCRIPTION
The XR16C2550 (2550) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16C2550 is an improved version of the PC16550
UART with higher operating speed and faster access
times. The 2550 provides enhanced UART functions
with 16 byte FIFO’s, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and
operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates from 50 bps to
4 Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
2550 is available in a 44-pin PLCC and 48-pin TQFP
packages. The 2550 is fabricated in an advanced
CMOS process capable of operating from 2.97 volt to
5.5 volt power supply.
APPLICATIONS
FEATURES
•
2.97 Volt to 5.5 Volt Operation
•
5 Volt Tolerant Inputs
•
Pin-to-pin compatible to Exar’s ST16C2450,
XR16L2550 and XR16L2750
•
Pin-to-pin compatible to TI’s TL16C752B on the 48-
TQFP package
•
Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
•
2 independent UART channels
■
■
■
■
■
■
■
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16C2550 B
LOCK
D
IAGRAM
Up to 4 Mbps with external clock of 64 MHz
Up to 1.5 Mbps data rate with a 24 MHz crystal
frequency
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable Receive FIFO interrupt trigger
levels
Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
•
Crystal oscillator or external clock input
•
48-TQFP and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
Reset
8- bit Data
Bus
Interface
*All inputs are 5V tolerant
2.97 V to 5.5V
GND
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
TXA , RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
UART Channel B
( same as Channel A )
Crystal Osc / Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
TXRDYA#
DSRA#
CTSA#
xr
REV. 1.0.1
VCC
RIA#
CDA#
48
45
43
42
41
40
38
47
46
44
39
37
NC
D4
D3
D2
D1
D0
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
NC
1
2
3
4
5
6
7
8
9
10
11
12
15
13
18
19
20
22
16
14
17
21
23
24
36
35
34
33
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
D0
D1
D2
D3
D4
D5
D6
D7
RXB
RXA
TXA
TXB
OP2B#
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
VCC
RIA#
CDA#
DSRA#
CTSA#
RESET
DTRB#
DTRA#
RTSA#
OP2A#
INTA
INTB
A0
A1
A2
CTSB#
RTSB#
RIB#
DSRB#
IOR#
XR16C2550
48-pin TQFP
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
17
18
19
20
XR16C2550IP
32
31
30
29
28
27
26
25
24
23
22
21
RXRDYB#
DSRB#
CDB#
GND
RIB#
RTSB#
TXRDYA#
DSRA#
CTSB#
XTAL2
XTAL1
IOW#
IOR#
CTSA#
NC
CDA#
RIA#
VCC
CSA#
CSB#
XTAL1
39
38
37
36
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
D4
D3
D2
D1
D0
44
43
42
41
40
6
5
4
3
2
1
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
XTAL2
IOW#
CDB#
GND
XR16C2550
44-pin PLCC
35
34
33
32
31 A0
30 A1
29 A2
IOW#
RXRDYB#
IOR#
GND
RIB#
RTSB#
ORDERING INFORMATION
P
ART
N
UMBER
XR16C2550IP
XR16C2550IJ
XR16C2550IM
P
ACKAGE
40-Lead PDIP
44-Lead PLCC
48-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active. See the XR16C2550IM for new designs.
Active
Active
DSRB#
CTSB#
XTAL1
XTAL2
CDB#
2
xr
REV. 1.0.1
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
40-PDIP 44-PLCC 48-TQFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
26
27
28
8
7
6
5
4
3
2
1
21
29
30
31
9
8
7
6
5
4
3
2
24
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
IO
I
Input/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on the
rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in
the device for data bus operation.
UART channel B select (active low) to enable UART channel B in
the device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel A. See
Table 2.
If it is not used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel A. See
Table 2.
If it is
not used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel B. See
Table 2.
If it is not used, leave it unconnected.
IOW#
18
20
15
I
CSA#
CSB#
INTA
14
15
30
16
17
33
10
11
30
I
I
O
INTB
29
32
29
O
TXRDYA#
-
1
43
O
RXRDYA#
-
34
31
O
TXRDYB#
-
12
6
O
3
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
N
AME
RXRDYB#
40-PDIP 44-PLCC 48-TQFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
-
23
18
O
D
ESCRIPTION
xr
REV. 1.0.1
UART channel B Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel B. See
Table 2.
If it is
not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
RXA
11
10
13
11
7
5
O
I
UART channel A Transmit Data. If it is not used, leave it uncon-
nected.
UART channel A Receive Data. Normal receive data input must idle
at logic 1 condition. If it is not used, tie it to VCC or pull it high via a
100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
UART channel A Data-Terminal-Ready (active low) or general pur-
pose output. If it is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
Output Port 2 Channel A - The output state is defined by the user
and through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output to a logic 0 when MCR[3] is set to a logic
1. INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTA output function-
ality. If it is not used at all, leave it unconnected.
UART channel B Transmit Data. If it is not used, leave it uncon-
nected.
UART channel B Receive Data. Normal receive data input must idle
at logic 1 condition. If it is not used, tie it to VCC or pull it high via a
100k ohm resistor.
UART channel B Request-to-Send (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
UART channel B Data-Terminal-Ready (active low) or general pur-
pose output. If it is not used, leave it unconnected.
RTSA#
CTSA#
32
36
36
40
33
38
O
I
DTRA#
DSRA#
33
37
37
41
34
39
O
I
CDA#
38
42
40
I
RIA#
39
43
41
I
OP2A#
31
35
32
O
TXB
RXB
12
9
14
10
8
4
O
I
RTSB#
CTSB#
24
25
27
28
22
23
O
I
DTRB#
34
38
35
O
4
xr
REV. 1.0.1
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
N
AME
DSRB#
40-PDIP 44-PLCC 48-TQFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
22
25
20
I
D
ESCRIPTION
UART channel B Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user
and through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output to a logic 0 when MCR[3] is set to a logic
1. INTB is set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTB output function-
ality. If it is not used, leave it unconnected.
CDB#
19
21
16
I
RIB#
23
26
21
I
OP2B#
13
15
9
O
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
16
17
35
18
19
39
13
14
36
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter
output will be held at logic 1, the receiver input will be ignored and
outputs are reset during reset period (see External Reset Condi-
tions).
VCC
GND
N.C.
40
20
-
44
22
-
42
17
12, 24,
25, 37
Pwr 2.97V to 5.5V power supply. All inputs are 5V tolerant.
Pwr Power supply common, ground.
No Connection.
N
OTE
:
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
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