MK48S80N15 datasheet, PDF - EEWORLD Datasheet

MK48S80N15: Description8KX8 CACHE TAG SRAM, 20ns, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28; Categorystorage storage; File Size397KB，14 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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MK48S80N15 Overview

8KX8 CACHE TAG SRAM, 20ns, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	DIP
package instruction	0.300 INCH, SKINNY, PLASTIC, DIP-28
Contacts	28
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	20 ns
Other features	TOTEM-POLE MATCH OUTPUT
JESD-30 code	R-PDIP-T28
JESD-609 code	e0
length	34.67 mm
memory density	65536 bit
Memory IC Type	CACHE TAG SRAM
memory width	8
Mixed memory types	N/A
Number of functions	1
Number of terminals	28
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum standby current	0.16 A
Maximum slew rate	0.16 mA
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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