PC8548EMZFAUJD-EP datasheet, PDF

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PC8548EMZFAUJD-EP: DescriptionMicroprocessor, 32-Bit, 1333MHz, CMOS, PBGA783, BGA-783; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，122 Pages; Manufacturere2v technologies

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PC8548EMZFAUJD-EP Overview

Microprocessor, 32-Bit, 1333MHz, CMOS, PBGA783, BGA-783

PC8548EMZFAUJD-EP Parametric

Parameter Name	Attribute value
Maker	e2v technologies
package instruction	BGA,
Reach Compliance Code	unknown
Other features	ALSO AVAILABLE 3.294MM SEATED-HEIGHT WITH STAMPED LID
Address bus width	16
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
length	29 mm
low power mode	YES
Number of terminals	783
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Maximum seat height	3.38 mm
speed	1333 MHz
Maximum supply voltage	1.155 V
Minimum supply voltage	1.045 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Data Sheet

PC8548E

PowerQUICC III Integrated Processor

Datasheet DS0831

FEATURES

•

Embedded e500 Core, Initial Offerings up to 1.2 GHz

– Dual Dispatch Superscalar, 7‐stage Pipeline Design with

out‐of‐order Issue and Execution

– 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1)

•

36‐bit Physical Addressing

•

Enhanced Hardware and Software Debug Support

•

Double‐precision Embedded Scalar and Vector Floating‐point

APUs

•

Memory Management Unit (MMU)

•

Integrated L1/L2 Cache

– L1 Cache‐32 KB Data and 32 KB Instruction Cache with

Line‐locking Support

– L2 Cache‐512 KB (8‐Way Set Associative); 512 KB/256

KB/128 KB/64 KB Can Be Used As SRAM

– L1 and L2 Hardware Coherency

– L2 Configurable As SRAM, Cache and I/O Transactions

Can Be Stashed Into L2 Cache Regions

•

Integrated DDR Memory Controller With Full ECC Support,

Supporting:

– 200 MHz Clock Rate (400 MHz Data Rate), 64‐bit,

2.5V/2.6V I/O, DDR SDRAM

•

Integrated Security Engine Supporting DES, 3DES, MD‐5, SHA‐

1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC‐4 Encryption

Algorithms

•

Four On‐chip Triple‐speed Ethernet Controllers (GMACs)

Supporting 10‐ and 100‐Mbps, and 1‐Gbps

Ethernet/IEEE*802.3 Networks with MII, RMII, GMII, RGMII,

RTBI and TBI Physical Interfaces

– TCP/IP Checksum Acceleration

– Advanced QoS Features

•

General‐purpose I/O (GPIO)

•

Serial RapidIO and PCI Express High‐speed Interconnect

Interfaces, Supporting

– Single x8 PCI Express, or Single x4 PCI Express and

Single 4x Serial RapidIO

•

On‐chip Network (OCeaN) Switch Fabric

•

Multiple PCI Interface Support

– 64‐bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O)

– 64‐bit PCI‐X Bus Controller (Up to 133 MHz, 3.3V I/O),

or Flexibility to Configure Two 32‐bit PCI Controllers

•

166 MHz, 32‐bit, 3.3V I/O, Local Bus with Memory

Controller

•

Integrated Four‐channel DMA Controller

•

Dual I2C and Dual Universal Asynchronous

Receiver/Transmitter (DUAR) Support

•

Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG

Test Access Port

•

1.1V Core Voltage with 3.3V and 2.5V I/O, 783‐pin HITCE

and PBGA Packages

DESCRIPTION

The PC8548E contains a Power Architecture

™

processor

core. The PC8548E integrates a processor that implements

the Power Architecture with system logic required for net‐

working, storage, and general‐purpose embedded

applications. For functional characteristics of the processor,

refer to the PC8548E Integrated Processor Preliminary Ref‐

erence Manual.

SCREENING

•

Full Military Temperature Range (T

= –55C, T

= +125C)

•

Industrial Temperature Range (T

= –40C, T

= +110C)

Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any

use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its

standard conditions of sale in respect of infringement of third party patents arising from the use of devices in accordance with information contained

herein.

e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc

Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492

Contact e2v by e‐mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres.

0831O–HIREL–01/16

PC8548EMZFAUJD-EP Related Products

	PC8548EMZFAUJD-EP	V62/14623-01XZ	PC8548EMZFATGD-EP	V62/14623-02XZ
Description	Microprocessor, 32-Bit, 1333MHz, CMOS, PBGA783, BGA-783	Microprocessor, 32-Bit, 1333MHz, CMOS, PBGA783, BGA-783	Microprocessor, 32-Bit, 1200MHz, CMOS, PBGA783, BGA-783	Microprocessor, 32-Bit, 1200MHz, CMOS, PBGA783, BGA-783
Maker	e2v technologies	e2v technologies	e2v technologies	e2v technologies
package instruction	BGA,	BGA-783	BGA,	BGA-783
Reach Compliance Code	unknown	compliant	compliant	compliant
Other features	ALSO AVAILABLE 3.294MM SEATED-HEIGHT WITH STAMPED LID	ALSO AVAILABLE 3.294MM SEATED-HEIGHT WITH STAMPED LID	ALSO AVAILABLE 3.294MM SEATED-HEIGHT WITH STAMPED LID	ALSO AVAILABLE 3.294MM SEATED-HEIGHT WITH STAMPED LID
Address bus width	16	16	16	16
bit size	32	32	32	32
boundary scan	YES	YES	YES	YES
maximum clock frequency	133 MHz	133 MHz	133 MHz	133 MHz
External data bus width	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES
JESD-30 code	S-PBGA-B783	S-PBGA-B783	S-PBGA-B783	S-PBGA-B783
length	29 mm	29 mm	29 mm	29 mm
low power mode	YES	YES	YES	YES
Number of terminals	783	783	783	783
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Maximum seat height	3.38 mm	3.38 mm	3.38 mm	3.38 mm
speed	1333 MHz	1333 MHz	1200 MHz	1200 MHz
Maximum supply voltage	1.155 V	1.155 V	1.155 V	1.155 V
Minimum supply voltage	1.045 V	1.045 V	1.045 V	1.045 V
Nominal supply voltage	1.1 V	1.1 V	1.1 V	1.1 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	29 mm	29 mm	29 mm	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR

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