C8051F336/7/8/9
Mixed-Signal Byte-Programmable EPROM MCU
Analog Peripherals
-
10-Bit ADC (‘F336/8 only)
•
•
•
•
•
Up to 200 ksps
Up to 20 external single-ended or differential inputs
VREF from on-chip VREF, external pin or V
DD
Internal or external start of conversion source
Built-in temperature sensor
Memory
-
768 bytes internal data RAM (256 + 512)
-
16 kB Flash; In-system programmable in 512-byte
Sectors (512 bytes are reserved)
Digital Peripherals
-
21 or 17 Port I/O; All 5 V tolerant with high sink
-
-
-
-
current
Pin-compatible with C8051F330 family of MCUs
Hardware enhanced UART, SMBus™ (I
2
C compati-
ble), and enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules and enhanced PWM
functionality
Real time clock mode using timer and crystal
-
-
10-Bit Current Output DAC (‘F336/8 only)
Comparator
•
•
Programmable hysteresis and response time
Configurable as interrupt or reset source
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost,
complete
development kit
-
Supply Voltage 2.7 to 3.6 V
-
Built-in voltage supply monitor
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Temperature Range: –40 to +85 °C
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
-
Clock Sources
-
24.5 MHz ±2% Oscillator
•
•
Supports crystal-less UART operation
Low-power suspend mode with fast wake time
-
-
-
80/20/40/10 kHz low-frequency, low-power
oscillator
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
20 or 24-Pin QFN (4 x 4 mm)
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CROSSBAR
Port 0
Port 1
P2.0–
P2.3*
P2.4*
*P2.1–2.4 QFN24 Only
10-bit
200 ksps
ADC
10-bit
Current
DAC
+
TEMP
SENSOR
‘F336/8 Only
–
VOLTAGE
COMPARATOR
24.5 MHz PRECISION
INTERNAL OSCILLATOR
LOW FREQUENCY INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR
WDT
Rev. 1.0 9/08
Copyright © 2008 by Silicon Laboratories
C8051F336/7/8/9
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051F336/7/8/9
2
Rev. 1.0
C8051F336/7/8/9
Table of Contents
1. System Overview ..................................................................................................... 15
2. Ordering Information ............................................................................................... 18
3. Pin Definitions.......................................................................................................... 19
4. QFN-20 Package Specifications ............................................................................. 23
5. QFN-24 Package Specifications ............................................................................. 25
6. Electrical Characteristics ........................................................................................ 27
6.1. Absolute Maximum Specifications..................................................................... 27
6.2. Electrical Characteristics ................................................................................... 28
6.3. Typical Performance Curves ............................................................................. 36
7. 10-Bit ADC (ADC0, C8051F336/8 only)................................................................... 37
7.1. Output Code Formatting .................................................................................... 38
7.2. Modes of Operation ........................................................................................... 38
7.2.1. Starting a Conversion................................................................................ 38
7.2.2. Tracking Modes......................................................................................... 39
7.2.3. Settling Time Requirements...................................................................... 40
7.3. Programmable Window Detector....................................................................... 44
7.3.1. Window Detector In Single-Ended Mode .................................................. 46
7.3.2. Window Detector In Differential Mode....................................................... 47
7.4. ADC0 Analog Multiplexer (C8051F336/8 only).................................................. 48
8. Temperature Sensor (C8051F336/8 only) .............................................................. 51
9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only) ............................................ 52
9.1. IDA0 Output Scheduling .................................................................................... 52
9.1.1. Update Output On-Demand ...................................................................... 52
9.1.2. Update Output Based on Timer Overflow ................................................. 53
9.1.3. Update Output Based on CNVSTR Edge ................................................. 53
9.2. IDAC Output Mapping ....................................................................................... 53
10. Voltage Reference (C8051F336/8 only) ................................................................ 56
11. Comparator0........................................................................................................... 58
11.1. Comparator Multiplexer ................................................................................... 63
12. CIP-51 Microcontroller........................................................................................... 65
12.1. Instruction Set.................................................................................................. 66
12.1.1. Instruction and CPU Timing .................................................................... 66
12.2. CIP-51 Register Descriptions .......................................................................... 71
13. Memory Organization ............................................................................................ 74
13.1. Program Memory............................................................................................. 75
13.1.1. MOVX Instruction and Program Memory ................................................ 75
13.2. Data Memory ................................................................................................... 75
13.2.1. Internal RAM ........................................................................................... 75
13.2.1.1. General Purpose Registers ............................................................ 76
13.2.1.2. Bit Addressable Locations .............................................................. 76
13.2.1.3. Stack ............................................................................................ 76
13.2.2. External RAM .......................................................................................... 76
Rev.1.0
3
C8051F336/7/8/9
14. Special Function Registers................................................................................... 78
15. Interrupts ................................................................................................................ 82
15.1. MCU Interrupt Sources and Vectors................................................................ 83
15.1.1. Interrupt Priorities.................................................................................... 83
15.1.2. Interrupt Latency ..................................................................................... 83
15.2. Interrupt Register Descriptions ........................................................................ 84
15.3. External Interrupts /INT0 and /INT1................................................................. 89
16. Flash Memory......................................................................................................... 91
16.1. Programming The Flash Memory .................................................................... 91
16.1.1. Flash Lock and Key Functions ................................................................ 91
16.1.2. Flash Erase Procedure ........................................................................... 91
16.1.3. Flash Write Procedure ............................................................................ 92
16.2. Non-volatile Data Storage ............................................................................... 92
16.3. Security Options .............................................................................................. 93
16.4. Flash Write and Erase Guidelines ................................................................... 95
16.4.1. V
DD
Maintenance and the V
DD
monitor .................................................. 95
16.4.2. PSWE Maintenance ................................................................................ 95
16.4.3. System Clock .......................................................................................... 96
17. Reset Sources ...................................................................................................... 100
17.1. Power-On Reset ............................................................................................ 101
17.2. Power-Fail Reset / VDD Monitor ................................................................... 102
17.3. External Reset ............................................................................................... 103
17.4. Missing Clock Detector Reset ....................................................................... 103
17.5. Comparator0 Reset ....................................................................................... 104
17.6. PCA Watchdog Timer Reset ......................................................................... 104
17.7. Flash Error Reset .......................................................................................... 104
17.8. Software Reset .............................................................................................. 104
18. Power Management Modes................................................................................. 106
18.1. Idle Mode....................................................................................................... 106
18.2. Stop Mode ..................................................................................................... 107
18.3. Suspend Mode .............................................................................................. 107
19. Oscillators and Clock Selection ......................................................................... 109
19.1. System Clock Selection................................................................................. 109
19.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 111
19.2.1. Internal Oscillator Suspend Mode ......................................................... 111
19.3. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 113
19.3.1. Calibrating the Internal L-F Oscillator.................................................... 113
19.4. External Oscillator Drive Circuit..................................................................... 114
19.4.1. External Crystal Example...................................................................... 116
19.4.2. External RC Example............................................................................ 117
19.4.3. External Capacitor Example.................................................................. 118
20. Port Input/Output ................................................................................................. 119
20.1. Port I/O Modes of Operation.......................................................................... 120
20.1.1. Port Pins Configured for Analog I/O...................................................... 120
20.1.2. Port Pins Configured For Digital I/O...................................................... 120
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Rev.1.0
C8051F336/7/8/9
20.1.3. Interfacing Port I/O to 5V Logic ............................................................. 121
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 122
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 122
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 122
20.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 123
20.3. Priority Crossbar Decoder ............................................................................. 124
20.4. Port I/O Initialization ...................................................................................... 126
20.5. Port Match ..................................................................................................... 129
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 131
21. SMBus................................................................................................................... 138
21.1. Supporting Documents .................................................................................. 139
21.2. SMBus Configuration..................................................................................... 139
21.3. SMBus Operation .......................................................................................... 139
21.3.1. Transmitter Vs. Receiver....................................................................... 140
21.3.2. Arbitration.............................................................................................. 140
21.3.3. Clock Low Extension............................................................................. 140
21.3.4. SCL Low Timeout.................................................................................. 140
21.3.5. SCL High (SMBus Free) Timeout ......................................................... 141
21.4. Using the SMBus........................................................................................... 141
21.4.1. SMBus Configuration Register.............................................................. 141
21.4.2. SMB0CN Control Register .................................................................... 145
21.4.2.1. Software ACK Generation ............................................................ 145
21.4.2.2. Hardware ACK Generation ........................................................... 145
21.4.3. Hardware Slave Address Recognition .................................................. 147
21.4.4. Data Register ........................................................................................ 150
21.5. SMBus Transfer Modes................................................................................. 151
21.5.1. Write Sequence (Master) ...................................................................... 151
21.5.2. Read Sequence (Master) ...................................................................... 152
21.5.3. Write Sequence (Slave) ........................................................................ 153
21.5.4. Read Sequence (Slave) ........................................................................ 154
21.6. SMBus Status Decoding................................................................................ 154
22. UART0 ................................................................................................................... 159
22.1. Enhanced Baud Rate Generation.................................................................. 160
22.2. Operational Modes ........................................................................................ 161
22.2.1. 8-Bit UART ............................................................................................ 161
22.2.2. 9-Bit UART ............................................................................................ 162
22.3. Multiprocessor Communications ................................................................... 163
23. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 167
23.1. Signal Descriptions........................................................................................ 168
23.1.1. Master Out, Slave In (MOSI)................................................................. 168
23.1.2. Master In, Slave Out (MISO)................................................................. 168
23.1.3. Serial Clock (SCK) ................................................................................ 168
23.1.4. Slave Select (NSS) ............................................................................... 168
23.2. SPI0 Master Mode Operation ........................................................................ 169
23.3. SPI0 Slave Mode Operation .......................................................................... 170
Rev.1.0
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