CY7C15632KV18
72-Mbit QDR
®
II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C15632KV18 – 4M x 18
Separate Independent Read and Write Data Ports
❐
Supports concurrent transactions
550 MHz Clock for High Bandwidth
4-word Burst for Reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1100 MHz) at 550 MHz
Available in 2.5 Clock Cycle Latency
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Data Valid Pin (QVLD) to indicate Valid Data on the Output
Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
Separate Port selects for Depth Expansion
Synchronous Internally Self-timed Writes
QDR
®
II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I Device with one Cycle Read Latency
when DOFF is asserted LOW
Available in x18 Configuration
Full Data Coherency, providing Most Current Data
Core V
DD
= 1.8V± 0.1V; I/O V
DDQ
= 1.4V to V
DD [1]
❐
Supports both 1.5V and 1.8V I/O supply
HSTL Inputs and Variable Drive HSTL Output Buffers
Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
JTAG 1149.1 compatible Test Access Port
Phase-Locked Loop (PLL) for Accurate Data Placement
■
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■
■
Functional Description
The CY7C15632KV18 is a 1.8V Synchronous Pipelined SRAM,
equipped with QDR II+ architecture. Similar to QDR II archi-
tecture, QDR II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words that burst sequentially into or out of the device. Because
data is transferred into and out of the device on every rising edge
of both input clocks (K and K), memory bandwidth is maximized
while simplifying system design by eliminating bus
“turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
550 MHz
550
920
500 MHz
500
850
450 MHz
450
780
400 MHz
400
710
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-54932 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 31, 2009
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CY7C15632KV18
Logic Block Diagram (CY7C15632KV18)
D
[17:0]
18
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Address
Register
Address
Register
20
A
(19:0)
1M x 18 Array
1M x 18 Array
1M x 18 Array
1M x 18 Array
K
K
CLK
Gen.
RPS
Control
Logic
DOFF
Read Data Reg.
CQ
72
V
REF
WPS
BWS
[1:0]
Control
Logic
36
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
QVLD
Pin Configuration
The pin configuration for CY7C15632KV18 follows.
[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C15632KV18 (4M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-54932 Rev. **
Page 2 of 22
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CY7C15632KV18
Pin Definitions
Pin Name
D
[17:0]
WPS
BWS
0
,
BWS
1
I/O
Pin Description
Input-
Data Input Signals.
Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous
Input-
Write Port Select
−
Active LOW.
Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Input-
Byte Write Select 0, 1, 2, and 3
−
Active LOW.
Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered. BWS
0
controls D
[8:0]
and BWS
1
controls
D
[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select ignores the corresponding byte of data and it is not written into the device.
Input-
Address Inputs.
Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4M x 18 (4 arrays each of 1M x 18) for CY7C15632KV18. Therefore, only 20 address inputs are needed
to access the entire memory array of CY7C15632KV18. These inputs are ignored when the appropriate
port is deselected.
Outputs-
Data Output Signals.
These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q
[17:0]
are automatically tristated.
Input-
Read Port Select
−
Active LOW.
Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
Valid output
indicator
Input Clock
Input Clock
Echo Clock
Echo Clock
Input
Valid Output Indicator.
The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[17:0]
. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[17:0]
.
Synchronous Echo Clock Outputs.
This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the
Switching Characteristics
on page 18.
Synchronous Echo Clock Outputs.
This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the
Switching Characteristics
on page 18.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[17:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL Turn Off
−
Active LOW.
Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR I timing.
TDO for JTAG
TCK Pin for JTAG
TDI Pin for JTAG
TMS Pin for JTAG
A
Q
[17:0]
RPS
QVLD
K
K
CQ
CQ
ZQ
DOFF
Input
TDO
TCK
TDI
TMS
Output
Input
Input
Input
Document Number: 001-54932 Rev. **
Page 3 of 22
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CY7C15632KV18
Pin Definitions
Pin Name
NC
I/O
N/A
N/A
N/A
(continued)
Pin Description
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
NC/144M
NC/288M
V
REF
V
DD
V
SS
V
DDQ
Input-
Reference
Power Supply
Power Supply Inputs to the Core of the Device
Ground
Ground for the Device
Power Supply
Power Supply Inputs for the Outputs of the Device
Document Number: 001-54932 Rev. **
Page 4 of 22
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CY7C15632KV18
Functional Overview
The CY7C15632KV18 is a synchronous pipelined Burst SRAM
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ completely
eliminates the need to “turnaround” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in two clock
cycles.
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to V
SS
then device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D
[x:0]
) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q
[x:0]
) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, NWS
[x:0]
, BWS
[x:0]
) inputs
pass through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C15632KV18 is described in the following sections.
When the read port is deselected, the CY7C15632KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D
[17:0]
is latched and stored into
the lower 18-bit write data register, provided BWS
[1:0]
are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D
[17:0]
is also stored
into the write data register, provided BWS
[1:0]
are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the positive input clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C15632KV18. A
write operation is initiated as described in the
Write Operations
section. The bytes that are written are determined by BWS
0
and
BWS
1
, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Read Operations
The CY7C15632KV18 is organized internally as four arrays of
1M x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the corre-
sponding lowest order 18-bit word of data is driven onto the
Q
[17:0]
using K as the output timing reference. On the subse-
quent rising edge of K, the next 18-bit data word is driven onto
the Q
[17:0]
. This process continues until all four 18-bit data words
have been driven out onto Q
[17:0]
. The requested data is valid
0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
Concurrent Transactions
The read and write ports on the CY7C15632KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows
a write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Document Number: 001-54932 Rev. **
Page 5 of 22
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