IBM PowerPC 750GX RISC Microprocessor
Revision Level DD1.X
Datasheet
Version: SA14-2765-02
September 2, 2005
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750GX_ds_title.fm SA14-2765-02
September 2, 2005
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
List of Figures ................................................................................................................ 5
List of Tables .................................................................................................................. 7
1. General Information .................................................................................................... 9
1.1 Features ............................................................................................................................................ 9
1.2 Design Highlights ............................................................................................................................ 11
1.3 Processor Version Register ............................................................................................................ 11
1.4 Part Number Information ................................................................................................................. 12
2. Overview .................................................................................................................... 13
2.1 Block Diagram ................................................................................................................................. 13
2.2 General Parameters ........................................................................................................................ 14
3. Electrical and Thermal Characteristics ................................................................... 15
3.1 DC Electrical Characteristics ...........................................................................................................
3.2 AC Electrical Characteristics ...........................................................................................................
3.3 Clock AC Specifications ..................................................................................................................
3.4 Spread Spectrum Clock Generator .................................................................................................
3.4.1 Design Considerations ..........................................................................................................
3.5 60x Bus Input AC Specifications .....................................................................................................
3.5.1 Input Setup Timing ................................................................................................................
3.6 60x Bus Output AC Specifications ..................................................................................................
3.6.1 IEEE 1149.1 AC Timing Specifications .................................................................................
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4. Dimensions and Signal Assignments ..................................................................... 29
4.1 Package ..........................................................................................................................................
4.1.1 Reduced-Lead package ........................................................................................................
4.1.1.1 Mechanical Specifications ..............................................................................................
4.1.1.2 Assembly Considerations ...............................................................................................
4.1.1.3 Board Layout Considerations .........................................................................................
4.2 Module Substrate Decoupling Voltage Assignments ......................................................................
4.3 Microprocessor Ball Placement .......................................................................................................
4.4 Pinout Listings .................................................................................................................................
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5. System Design Information ..................................................................................... 46
5.1 Core Voltage Operation ..................................................................................................................
5.2 Low Voltage Operation at Lower Frequency ...................................................................................
5.2.1 Overview ................................................................................................................................
5.2.2 Restrictions and Considerations for PLL Configuration .........................................................
5.2.2.1 Configuration Restriction on Frequency Transitions ......................................................
5.2.3 PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................
5.2.4 PLL Configuration ..................................................................................................................
5.3 PLL Power Supply Filtering .............................................................................................................
5.4 Decoupling Recommendations .......................................................................................................
5.5 Connection Recommendations .......................................................................................................
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Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
5.6 Output Buffer DC Impedance ..........................................................................................................
5.6.1 Input/Output Usage ................................................................................................................
5.7 Thermal Management Information ..................................................................................................
5.7.1 Thermal Assist Unit ................................................................................................................
5.7.2 Minimum Heat Sink Requirements ........................................................................................
5.7.3 Internal Package Conduction Resistance ..............................................................................
5.7.4 Adhesives and Thermal Interface Materials ...........................................................................
5.8 Heat-Sink Selection Example ..........................................................................................................
5.9 Operational and Design Considerations ..........................................................................................
5.9.1 Level Protection .....................................................................................................................
5.9.2 64-Bit or 32-Bit Data Bus Mode .............................................................................................
5.9.3 I/O Voltage Mode Selection ...................................................................................................
5.9.4 QACK Signal Implementation for Selected Features .............................................................
5.9.4.1 Precharge Duration Selection and Application ...............................................................
5.9.4.2 Processor Debug System Enablement when Implementing Precharge Selection .........
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Revision Log ................................................................................................................. 73
Page 4 of 73
750GX_dsTOC.fm SA14-2765-02
September 2, 2005
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
List of Figures
Figure 2-1.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
IBM PowerPC 750GX RISC Microprocessor Block Diagram ................................................. 13
SYSCLK Input Timing Diagram .............................................................................................. 18
Linear Sweep Modulation Profile ........................................................................................... 19
Input Timing Definition ........................................................................................................... 21
Input Timing Diagram ............................................................................................................. 21
Mode Select Input Timing Diagram ........................................................................................ 22
Output Valid Timing Definition ................................................................................................ 24
Output Timing Diagram for IBM PowerPC 750GX RISC Microprocessor .............................. 25
JTAG Clock Input Timing Diagram ......................................................................................... 27
TRST Timing Diagram ........................................................................................................... 27
Figure 3-10. Boundary-Scan Timing Diagram ............................................................................................ 27
Figure 3-11. Test Access Port Timing Diagram .......................................................................................... 28
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Mechanical Dimensions, Standard Package .......................................................................... 31
Mechanical Dimensions, ROHS-Compatible Package .......................................................... 33
Module Substrate Decoupling Voltage Assignments ............................................................. 35
PowerPC 750GX Microprocessor Ball Placement ................................................................. 36
Single PLL Power Supply Filter Circuit with A1VDD Pin and A2VDD Pin Tied to GND ......... 51
PLL Power Supply Filter Circuit with Two AVDD Pins and One Ferrite Bead ........................ 51
Dual PLL Power Supply Filter Circuits ................................................................................... 52
Orientation and Layout of the 750GX Decoupling Capacitors ............................................... 54
Driver Impedance Measurement ............................................................................................ 55
IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector ........................ 61
Package Exploded Cross-Sectional View with Several Heat-Sink Options ........................... 62
C4 Package with Heat Sink Mounted to a Printed-Circuit Board ........................................... 65
Thermal Performance of Select Thermal Interface Material .................................................. 66
Figure 5-10. Example of a Pin-Fin Heat-Sink-to-Ambient Thermal Resistance versus Airflow Velocity .... 68
750GX_dsLOF.fm SA14-2765-02
September 2, 2005
List of Figures
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