Cache SRAM, 64KX18, CMOS, PQCC52
| Parameter Name | Attribute value |
| Maker | Paradigm Technology Inc |
| package instruction | , |
| Reach Compliance Code | unknown |
| ECCN code | 3A991.B.2.A |
| JESD-30 code | S-PQCC-J52 |
| memory density | 1179648 bit |
| Memory IC Type | CACHE SRAM |
| memory width | 18 |
| Number of functions | 1 |
| Number of ports | 1 |
| Number of terminals | 52 |
| word count | 65536 words |
| character code | 64000 |
| Operating mode | SYNCHRONOUS |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| organize | 64KX18 |
| Output characteristics | 3-STATE |
| Exportable | YES |
| Package body material | PLASTIC/EPOXY |
| Package shape | SQUARE |
| Package form | CHIP CARRIER |
| Parallel/Serial | PARALLEL |
| Certification status | Not Qualified |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal form | J BEND |
| Terminal location | QUAD |
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