Features
•
Serial Peripheral Interface (SPI) Compatible
•
Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
•
Medium-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7V to 5.5V)
Extended Temperature Range
−40°C
to +125°C
5.0 MHz Clock Rate
8-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
8-lead JEDEC SOIC and 8-lead TSSOP Packages
SPI Automotive
Temperature
Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
Description
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically-eras-
able programmable read-only memory (EEPROM) organized as 128/256/512 words of
8 bits each. The device is optimized for use in many automotive applications where
low-power and low-voltage operation are essential. The AT25010A/020A/040A is
available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages.
The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate program enable and program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 1.
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
AT25010A
AT25020A
AT25040A
8-lead SOIC
8-lead
TSSOP
5087D–SEEPR–3/07
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Figure 1.
Block Diagram
128/256/
512 x
8
2
AT25010A/020A/040A
5087D–SEEPR–3/07
AT25010A/020A/040A
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
Table 3.
DC Characteristics
Applicable over recommended operating range from: T
A
=
−40°C
to +125°C. V
CC
= +2.7V to +5.5V
Symbol
V
CC1
I
CC1
I
CC2
I
CC3
I
SB1(1)
I
SB2(1)
I
IL
I
OL
V
IL(2)
V
IH(2)
V
OL1
V
OH1
V
OL2
V
OH2
Note:
Parameter
Supply Voltage
Supply Current
Supply Current
Supply Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
3.6V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
3.6V
I
OL
= 2.0 mA
I
OH
=
−1.0
mA
I
OL
= 0.15 mA
I
OH
=
−100
µA
V
CC
– 0.2
V
CC
– 0.8
0.2
V
CC
= 5.0V at 1 MHz, SO = Open, Read
V
CC
= 5.0V at 2 MHz, SO = Open,
Read, Write
V
CC
= 5.0V at 5 MHz, SO = Open,
Read, Write
V
CC
= 2.7V
V
CC
= 5.0V
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
CS = V
CC
CS = V
CC
−0.6
−0.6
−0.6
V
CC
x 0.7
Test Condition
Min
2.7
Max
5.5
3.0
6.0
6.0
3.0
5.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
V
mA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
1. Worst case measured at 125°C
2. V
IL
min and V
IH
max are reference only and are not tested.
3
5087D–SEEPR–3/07
Table 4.
AC Characteristics
Applicable over recommended operating range from T
A
=
−40°C
to +125°C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Write Cycle Time
5.0V, 25°C, Page Mode
Voltage
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
2.7–5.5
1M
40
40
80
80
80
5
20
40
40
0
0
0
40
80
80
5
40
ns
ns
ns
ns
ns
ns
ms
Write Cycles
Min
0
Max
5.0
2
2
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
f
SCK
t
RI
t
FI
t
WH
t
WL
t
CS
t
CSS
t
CSH
t
SU
t
H
t
HD
t
CD
t
V
t
HO
t
LZ
t
HZ
t
DIS
t
WC
Endurance
(1)
Note:
1. This parameter is characterized and is not 100% tested.
4
AT25010A/020A/040A
5087D–SEEPR–3/07
AT25010A/020A/040A
Serial Interface
Description
MASTER:
The device that generates the serial clock.
S L AV E :
B e c a u s e t h e s e r i a l c l o c k p i n ( S C K ) i s a l w a y s a n i n p u t , t h e
AT25010A/020A/040A always operates as a slave.
TRANSMITTER/RECEIVER:
The AT25010A/020A/040A has separate pins designated
for data transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the Read and Write instructions.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the
AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance
state until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT:
The AT25010A/020A/040A is selected when the CS pin is low. When
the device is not selected, data will not be accepted via the SI pin, and the serial output
pin (SO) will remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the
AT25010A/020A/040A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited. WP
going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
5
5087D–SEEPR–3/07
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