EP20K200CQ208I-7 datasheet, PDF

EP20K200CQ208I-7: DescriptionLoadable PLD, 1.6ns, CMOS, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size1MB，90 Pages; ManufacturerAltera (Intel)

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EP20K200CQ208I-7 Overview

Loadable PLD, 1.6ns, CMOS, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	FQFP, QFP208,1.2SQ,20
Contacts	208
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
length	28 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	136
Number of entries	128
Number of logical units	8320
Output times	128
Number of terminals	208
organize	4 DEDICATED INPUTS, 136 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
power supply	1.8,1.8/3.3 V
Programmable logic type	LOADABLE PLD
propagation delay	1.6 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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