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K4F660812E-TI50

Description
Fast Page DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32
Categorystorage    storage   
File Size172KB,20 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K4F660812E-TI50 Overview

Fast Page DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

K4F660812E-TI50 Parametric

Parameter NameAttribute value
MakerSAMSUNG
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts32
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFAST PAGE
Maximum access time50 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 codeR-PDSO-G32
length20.95 mm
memory density67108864 bit
Memory IC TypeFAST PAGE DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count8388608 words
character code8000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width10.16 mm
Industrial Temperature
K4F660812E,K4F640812E
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) ar e
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-
thermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung
′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
CMOS DRAM
FEATURES
• Part Identification
- K4F660812E-JI/P(3.3V, 8K Ref., SOJ)
- K4F640812E-JI/P(3.3V, 4K Ref., SOJ)
- K4F660812E-TI/P(3.3V, 8K Ref., TSOP)
- K4F640812E-TI/P(3.3V, 4K Ref., TSOP)
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
Active Power Dissipation
Unit : mW
Speed
-45
-50
-60
Refresh Cycles
Part
NO.
K4F660812E*
K4F640812E
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
CAS
W
Control
Clocks
Vcc
Vss
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V
±0.3V
power supply
Industrial Temperature operating
( -40~85
°C
)
4K
432
396
360
8K
324
288
252
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
Refresh Control
Refresh Counter
Memory Array
8,388,608 x 8
Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Performance Range
Speed
-45
-50
-60
Refresh Timer
Row Decoder
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
80ns
90ns
110ns
t
PC
31ns
35ns
40ns
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.

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