M27W800
8 Mbit (1Mb x 8 or 512Kb x 16)
Low Voltage UV EPROM and OTP EPROM
s
2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
ACCESS TIME:
– 90ns at V
CC
= 3.0V to 3.6V
– 100ns at V
CC
= 2.7V to 3.6V
42
42
s
s
BYTE-WIDE or WORD-WIDE
CONFIGURABLE
8 Mbit MASK ROM REPLACEMENT
LOW POWER CONSUMPTION
– Active Current 30mA at 8MHz
– Standby Current 15µA
1
1
FDIP42W (F)
PDIP42 (B)
s
s
s
s
s
PROGRAMMING VOLTAGE: 12.5V ± 0.25V
PROGRAMMING TIME: 50µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B2h
Figure 1. Logic Diagram
PLCC44 (K)
DESCRIPTION
The M27W800 is a low voltage 8 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage. It is organised as either 1 Mbit
words of 8 bit or 512 Kbit words of 16 bit. The pin-
out is compatible with a 8 Mbit Mask ROM.
The M27W800 operates in the read mode with a
supply voltage as low as 2.7V. The decrease in
operating power allows either a reduction of the
size of the battery or an increase in the time be-
tween battery recharges.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27W800 is offered in PDIP42 and PLCC44 pack-
age.
VCC
19
A0-A18
15
Q15A–1
Q0-Q14
E
G
BYTEVPP
M27W800
VSS
AI03601
March 2000
1/15
M27W800
Figure 2A. DIP Connections
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
42
2
41
3
40
4
39
5
38
6
37
7
36
35
8
9
34
10
33
M27W800
32
11
31
12
30
13
29
14
28
15
27
16
26
17
18
25
24
19
20
23
22
21
AI03602
Figure 2B. LCC Connections
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
A5
A6
A7
A17
A18
VSS
NC
A8
A9
A10
A11
1 44
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A–1
Q7
Q14
Q6
12
M27W800
34
23
Q9
Q2
Q10
Q3
Q11
NC
VCC
Q4
Q12
Q5
Q13
AI03603
Table 1. Signal Names
A0-A18
Q0-Q7
Q8-Q14
Q15A–1
E
G
BYTEV
PP
V
CC
V
SS
NC
Address Inputs
Data Outputs
Data Outputs
Data Output / Address Input
Chip Enable
Output Enable
Byte Mode / Program Supply
Supply Voltage
Ground
Not Connected Internally
DEVICE OPERATION
The operating modes of the M27W800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27W800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
PP
pin is at V
IL
the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
IL
the
lower 8 bits of the 16 bit data are selected and with
A–1 at V
IH
the upper 8 bits of the 16 bit data are
selected.
The M27W800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
2/15
M27W800
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
E
V
IL
V
IL
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
BYTEV
PP
V
IH
V
IL
V
IL
X
V
PP
V
PP
V
PP
X
V
IH
A9
X
X
X
X
X
X
X
X
V
ID
Q15A–1
Data Out
V
IH
V
IL
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Code
Q14-Q8
Data Out
Hi-Z
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Q7-Q0
Data Out
Data Out
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q15
and
Q7
0
1
Q14
and
Q6
0
0
Q13
and
Q5
1
1
Q12
and
Q4
0
1
Q11
and
Q3
0
0
Q10
and
Q2
0
0
Q9
and
Q1
0
1
Q8
and
Q0
0
0
Hex Data
20h
B2h
3/15
M27W800
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance (except BYTEV
PP
)
Input Capacitance (BYTEV
PP
)
Output Capacitance
Test Condition
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
120
12
Unit
pF
pF
pF
Note: 1. Sampled only, not 100% tested.
4/15
M27W800
Table 7. Read Mode DC Characteristics
(1)
(T
A
= –40 to 85 °C; V
CC
= 2.7 to 3.6V; V
PP
= V
CC
)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 8MHz, V
CC
≤
3.6V
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
≤
3.6V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –400µA
2.4
E = V
IH
E > V
CC
– 0.2V, V
CC
≤
3.6V
V
PP
= V
CC
–0.6
0.7V
CC
20
1
15
10
0.2V
CC
V
CC
+ 0.5
0.4
mA
mA
µA
µA
V
V
V
V
Min
Max
±1
±10
30
Unit
µA
µA
mA
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Standby Mode
The M27W800 has a standby mode which reduc-
es the supply current from 20mA to 20µA with low
voltage operation V
CC
≤
3.6V, see Read Mode DC
Characteristics table for details.The M27W800 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between V
CC
and V
SS
. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween V
CC
and V
SS
for every eight devices. This
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
5/15
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