ADVANCE
512K x 32
DDR SGRAM
DOUBLE DATA
RATE SGRAM
FEATURES
• Internal, pipelined double data rate (DDR) architec-
ture; two data accesses per clock cycle
• Bidirectional, intermittent data strobe (DQS) is
transmitted/received with data and used in capturing
data at the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CLK and CLK#)
• DLL aligns DQ and DQS transitions with CLK
transitions (JEDEC mode only)
• Commands entered on each positive CLK edge; data
referenced to both edges of DQS
• Four internal banks for concurrent operation:
128K x 32 x 4 banks, with 9 row- and 8 column-address
bits per bank
• Burst lengths: 2, 4, 8 or full page
• AUTO PRECHARGE option for each burst access
• 16-column BLOCK WRITE
• BYTE WRITE operation (masking via DM0-3)
• Auto Refresh and Self Refresh Modes
• 16ms, 2,048-cycle auto refresh (7.8µs/row)
• 2.5V (SSTL_2-compatible) I/O
• +2.5V
±0.2V
V
DD
; +2.5V
±0.2V
V
DD
Q
MT45V512K32 – 128K x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View)
100-Pin TQFP*
DQ2
V
SS
Q
DQ1
DQ0
V
DD
V
DD
Q
DQS
RFU (DQS#)
V
SS
Q
DNU
NC
NC
NC
NC
V
DD
Q
V
SS
DQ31
DQ30
V
SS
Q
DQ29
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
OPTIONS
MARKING
-6
-7
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
V
REF
DM3
DM1
CLK
CLK#
CKE
DSF
A8/AP
• Timing - Cycle Time (Clock Frequency)
6ns (≤ 167 MHz) @ CL = 3
6.5ns (≤ 150 MHz) @ CL = 3
• Plastic Package
100-pin TQFP (0.65mm lead pitch)
LG
• Part Number Example: MT45V512K32LG-6
KEY TIMING PARAMETERS
(JEDEC MODE)
SPEED
GRADE
-6
-7
CLOCK FREQUENCY (1/
t
CK)
CL = 2*
CL = 3*
111 MHz
100 MHz
167 MHz
150 MHz
ACCESS
TIME
±0.6ns
±0.65ns
DQ-DQS
SKEW
±0.45ns
±0.5ns
*JEDEC-standard MS-026 BHA (LQFP)
16Mb DDR SGRAM PART NUMBER
PART NUMBER
MT45V512K32LG
ARCHITECTURE
512K x 32
* CL = CAS (READ) latency
512K x 32 DDR SGRAM
16MDDRSGBW.p65 – Rev. 7/98
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
A0
A1
A2
A3
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
A4
A5
A6
A7
512K x 32
Configuration
128K x 32 x 4 banks
Refresh Count
2K
Row Addressing
512 (A0-A8)
Bank Addressing
4 (BA0, BA1)
Column Addressing
256 (A0-A7)
ADVANCE
512K x 32
DDR SGRAM
GENERAL DESCRIPTION
The 16Mb DDR SGRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It is
internally configured as a quad-bank DRAM, with each
4,194,304-bit bank organized as 512 rows by 256 columns by
32 bits.
The 16Mb DDR SGRAM uses an internal, pipelined
double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n
prefetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read
or write access for the 16Mb DDR SGRAM consists of a
single 64-bit, one-clock-cycle data transfer at the internal
DRAM core and two corresponding 32-bit, one-half-clock-
cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transferred exter-
nally, along with data, for use in data capture at the receiver.
DQS is an intermittent strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for READs
and center-aligned with data for WRITEs.
The 16Mb DDR SGRAM operates from a differential
clock (CLK and CLK#; the crossing of CLK going HIGH and
CLK# going LOW will be referred to as the postive edge of
CLK). Commands (address and control signals) are regis-
tered at every positive edge of CLK. Input data is registered
on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0, BA1 select the bank; A0-A8 select
the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
The DDR SGRAM provides for programmable READ or
WRITE burst lengths of 2, 4, or 8 locations, or the full page.
An AUTO PRECHARGE function may be enabled to pro-
vide a self-timed row precharge that is initiated at the end
of the burst sequence.
As with standard SGRAMs, the pipelined, multibank
architecture of DDR SGRAMs allows for concurrent opera-
tion, thereby providing high effective bandwidth by hiding
row precharge and activation time.
DDR SGRAMs differ from DDR SDRAMs in configura-
tion and by providing 16-column BLOCK WRITE and
full-page burst capability. The quad-bank pipelined
architecture, combined with the additional graphics func-
tions, results in a device particularly well suited to
high-performance graphics applications or other high-
bandwidth applications.
The 16Mb DDR SGRAM is designed to operate in 2.5V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for
SSTL_2. All outputs are SSTL_2, Class II compatible.
512K x 32 DDR SGRAM
16MDDRSGBW.p65 – Rev. 7/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
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