K4D263238K-UC500 datasheet, PDF

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K4D263238K-UC500: DescriptionDDR DRAM, 4MX32, 0.7ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, TQFP-100; Categorystorage storage; File Size387KB，19 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4D263238K-UC500 Overview

DDR DRAM, 4MX32, 0.7ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, TQFP-100

K4D263238K-UC500 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	QFP
package instruction	TQFP, TQFP100,.7X.9,25
Contacts	100
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PQFP-G100
length	20 mm
memory density	134217728 bit
Memory IC Type	DDR DRAM
memory width	32
Humidity sensitivity level	2
Number of functions	1
Number of ports	1
Number of terminals	100
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	65 °C
Minimum operating temperature
organize	4MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Encapsulate equivalent code	TQFP100,.7X.9,25
Package shape	RECTANGULAR
Package form	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8,FP
Maximum standby current	0.02 A
Maximum slew rate	0.358 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm

K4D263238K-UC500 Preview

K4D263238K

128M GDDR SDRAM

128Mbit GDDR SDRAM

Revision 1.3

December 2007

Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

- 1/17 -

Rev. 1.3 December 2007

K4D263238K

Revision History

Revision

1.0

1.1

1.2

1.3

Month

January

July

October

December

Year

2007

- Release revision 1.0 SPEC

History

128M GDDR SDRAM

- Revised comment about voltage of power up sequence

- Revised ICC2P current to 20mA

- Revised IBIS SPEC

- Added the comment of Halogen-free supporting

- 2/17 -

Rev. 1.3 December 2007

K4D263238K

128M GDDR SDRAM

1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

FEATURES

• 2.5V ± 5% power supply for device operation

• 2.5V ± 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• MRS cycle with address key programs

-. Read latency 3 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• Differential clock input

• Write Interrupted by Read function

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• Auto & Self refresh

• 32ms refresh period (4K cycle)

•

Pb-free & Halogen-free 100pin TQFP2 Package

•

RoHS compliant

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

ORDERING INFORMATION

Part NO.

K4D263238K-U

*1

C40

K4D263238K-UC50

Max Freq.

250MHz

200MHz

Max Data Rate

500Mbps/pin

400Mbps/pin

Interface

SSTL_2

Package

100 TQFP

Pb-free & Halogen-free

*1

Note 1 : 128Mb K-die GDDR x32 100TQFP DRAMs support Pb-free & Halogen-free package with Pb-free package code(-U).

GENERAL DESCRIPTION

FOR 1M x 32Bit x 4 Bank DDR SDRAM

The K4D263238K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by

32 bits, fabricated with SAMSUNG

′

s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

- 3/17 -

Rev. 1.3 December 2007

K4D263238K

PIN CONFIGURATION

(Top View)

128M GDDR SDRAM

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

DQ29

VSSQ

DQ30

DQ31

VSS

VDDQ

N.C

VSSQ

RFU

DQS

VDDQ

VDD

DQ0

DQ1

VSSQ

DQ2

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

10

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

11

1

2

3

4

5

6

7

8

9

A8(AP)

VDDQ

VSSQ

VREF

DQ10

DQ28

DQ27

DQ26

DQ25

DQ24

DQ15

DQ14

DQ13

DQ12

DQ11

VDD

DM3

DM1

DQ9

DQ8

CKE

VSS

CK

NC

A7

A6

A5

A4

VSS

A9

N.C

A11

A10

VDD

A3

A2

A1

A0

100 Pin TQFP

20 x 14

mm

2

0.65mm pin Pitch

42

41

40

39

38

37

36

35

34

33

32

31

DQ16

DQ17

DQ18

DQ19

VDD

DQ20

DQ21

DQ22

DQ23

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

DM2

VSS

CAS

VSSQ

VDDQ

VSSQ

PIN DESCRIPTION

CK,CK

CKE

CS

RAS

CAS

WE

DQS

DMi

RFU

Differential Clock Input

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Data Strobe

Data Mask

Reserved for Future Use

BA

0

, BA

1

A

0

~A

11

DQ

0

~ DQ

31

V

DD

V

SS

V

DDQ

V

SSQ

Bank Select Address

Address Input

Data Input/Output

Power

Ground

Power for DQ

′

s

Ground for DQ

′

s

VDDQ

- 4/17 -

Rev. 1.3 December 2007

RAS

BA0

BA1

WE

CS

K4D263238K

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

CK, CK

*1

Input

Type

128M GDDR SDRAM

Function

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

DQ

′

s and DM

′

s that are sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Data input and output are synchronized with both edge of DQS.

Data In mask. Data In is masked by DM Latency=0 when DM is high

in burst write. DM

0

for DQ

0

~ DQ

7,

DM

1

for DQ

8

~ DQ

15,

DM

2

for

DQ

16

~ DQ

23,

DM

3

for DQ

24

~ DQ

31.

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA

0

~ RA

11

, Column addresses : CA

0

~ CA

7

.

Column address CA

8

is used for auto precharge.

Power and ground for the input buffers and core logic.

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

Reference voltage for inputs, used for SSTL interface.

CKE

Input

CS

Input

RAS

CAS

WE

DQS

DM

0

~ DM

3

DQ

0

~ DQ

31

BA

0

, BA

1

A

0

~ A

11

V

DD

/V

SS

V

DDQ

/V

SSQ

V

REF

Input

Input/Output

Input

Input/Output

Input

Power Supply

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply V

REF

to CK pin.

- 5/17 -

Rev. 1.3 December 2007

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K4D263238K-UC500 Related Products

	K4D263238K-UC500	K4D263238K-UC400
Description	DDR DRAM, 4MX32, 0.7ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, TQFP-100	DDR DRAM, 4MX32, 0.6ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, TQFP-100
Is it Rohs certified?	conform to	conform to
Maker	SAMSUNG	SAMSUNG
Parts packaging code	QFP	QFP
package instruction	TQFP, TQFP100,.7X.9,25	TQFP, TQFP100,.7X.9,25
Contacts	100	100
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.7 ns	0.6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	250 MHz	250 MHz
I/O type	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8
JESD-30 code	R-PQFP-G100	R-PQFP-G100
length	20 mm	20 mm
memory density	134217728 bit	134217728 bit
Memory IC Type	DDR DRAM	DDR DRAM
memory width	32	32
Humidity sensitivity level	2	2
Number of functions	1	1
Number of ports	1	1
Number of terminals	100	100
word count	4194304 words	4194304 words
character code	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	65 °C	65 °C
organize	4MX32	4MX32
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TQFP	TQFP
Encapsulate equivalent code	TQFP100,.7X.9,25	TQFP100,.7X.9,25
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
power supply	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified
refresh cycle	4096	4096
Maximum seat height	1.2 mm	1.2 mm
self refresh	YES	YES
Continuous burst length	2,4,8,FP	2,4,8,FP
Maximum standby current	0.02 A	0.02 A
Maximum slew rate	0.358 mA	0.412 mA
Maximum supply voltage (Vsup)	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	40	40
width	14 mm	14 mm

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