SST49LF040A-33-4C-NH datasheet, PDF

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SST49LF040A-33-4C-NH: DescriptionFlash, 512KX8, 11ns, PQCC32, PLASTIC, LCC-32; Categorystorage storage; File Size601KB，52 Pages; ManufacturerSilicon Laboratories Inc

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SST49LF040A-33-4C-NH Overview

Flash, 512KX8, 11ns, PQCC32, PLASTIC, LCC-32

SST49LF040A-33-4C-NH Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Parts packaging code	QFJ
package instruction	QCCJ,
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	11 ns
Other features	120 NANO SECOND ACCESS TIME IN PARALLEL PROGRAMMING MODE
JESD-30 code	R-PQCC-J32
length	13.97 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3.55 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.43 mm

SST49LF040A-33-4C-NH Preview

3 Mbit / 4 Mbit / 8 Mbit LPC Flash

SST49LF030A / SST49LF040A / SST49LF080A

SST49LF030A / SST49LF040A / SST49LF080A3 Mb / 4 Mb / 8 Mbit LPC Flash

Advance Information

FEATURES:

• LPC Interface Flash

– SST49LF030A: 384K x8 (3 Mbit)

SST49LF040A: 512K x8 (4 Mbit)

SST49LF080A: 1024K x8 (8 Mbit)

• Conforms to Intel LPC Interface Specification 1.0

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 64 KByte overlay blocks

– 64 KByte Top boot block protection

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 6 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

SST49LF030A: 6 seconds (typical)

SST49LF040A: 8 seconds (typical)

SST49LF080A: 16 seconds (typical)

– Single-pulse Program or Erase

– Internal timing generation

• Two Operational Modes

– Low Pin Count (LPC) Interface mode for

in-system operation

– Parallel Programming (PP) Mode for fast production

programming

• LPC Interface Mode

– 5-signal communication interface supporting

byte Read and Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write protect

for entire chip and/or top boot block

– Standard SDP Command Set

– Data# Polling and Toggle Bit for End-of-Write

detection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

– 11-pin multiplexed address and 8-pin data

I/O interface

– Supports fast programming In-System on pro-

grammer equipment

• CMOS and PCI I/O Compatibility

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

PRODUCT DESCRIPTION

The SST49LF0x0A flash memory devices are designed to

interface with the LPC bus for PC and Internet Appliance

application in compliance with Intel Low Pin Count (LPC)

Interface Specification 1.0. Two interface modes are sup-

ported by the SST49LF0x0A: LPC mode for In-System

operations and Parallel Programming (PP) mode to inter-

face with programming equipment.

The SST49LF0x0A flash memory devices are manufac-

tured with SST’s proprietary, high performance SuperFlash

Technology. The split-gate cell design and thick oxide tun-

neling injector attain better reliability and manufacturability

compared with alternate approaches. The SST49LF0x0A

devices significantly improve performance and reliability,

while lowering power consumption. The SST49LF0x0A

devices write (Program or Erase) with a single 3.0-3.6V

power supply. It uses less energy during Erase and Pro-

gram than alternative flash memory technologies. The total

energy consumed is a function of the applied voltage, cur-

rent and time of application. Since for any give voltage

range, the SuperFlash technology uses less current to pro-

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554

gram and has a shorter erase time, the total energy con-

sumed during any Erase or Program operation is less than

alternative flash memory technologies. The SST49LF0x0A

products provide a maximum Byte-Program time of 20

µsec. The entire memory can be erased and programmed

byte-by-byte typically in 6 seconds for SST49LF030A, 8

seconds for the SST49LF040A and 16 seconds for the

SST49LF080A, when using status detection features such

as Toggle Bit or Data# Polling to indicate the completion of

Program operation. The SuperFlash technology provides

fixed Erase and Program time, independent of the number

of Erase/Program cycles that have performed. Therefore

the system software or hardware does not have to be cali-

brated or correlated to the cumulative number of Erase

cycles as is necessary with alternative flash memory tech-

nologies, whose Erase and Program time increase with

accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the

SST49LF0x0A devices are offered in 32-lead TSOP and

32-lead PLCC packages. See Figures 1 and 2 for pin

assignments and Table 1 for pin descriptions.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Intel is a registered trademark of Intel Corporation.

These specifications are subject to change without notice.

3 Mbit / 4 Mbit / 8 Mbit LPC Flash

SST49LF030A / SST49LF040A / SST49LF080A

Advance Information

TABLE OF CONTENTS

PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DEVICE MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PRODUCT IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MODE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LFRAME# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TBL#, WP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INIT#, RST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

System Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Response To Invalid Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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3 Mbit / 4 Mbit / 8 Mbit LPC Flash

SST49LF030A / SST49LF040A / SST49LF080A

Advance Information

PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chip-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data# Polling (DQ

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Toggle Bit (DQ

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Protection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Software Data Protection (SDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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3 Mbit / 4 Mbit / 8 Mbit LPC Flash

SST49LF030A / SST49LF040A / SST49LF080A

Advance Information

LIST OF FIGURES

FIGURE 1: Pin Assignments for 32-lead TSOP (8mm x 14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE 2: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE 3: Device Memory Map for SST49LF030A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FIGURE 4: Device Memory Map for SST49LF040A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FIGURE 5: Device Memory Map for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FIGURE 6: LPC Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FIGURE 7: LPC Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FIGURE 8: Program Command Sequence (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FIGURE 9: Data# Polling Command Sequence (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

FIGURE 10: Toggle Bit Command Sequence (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FIGURE 11: Sector-Erase Command Sequence (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FIGURE 12: Block-Erase Command Sequence (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

FIGURE 13: Register Readout Command Sequence (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

FIGURE 14: LCLK Waveform (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FIGURE 15: Reset Timing Diagram (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE 16: Output Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FIGURE 17: Input Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FIGURE 18: Reset Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FIGURE 19: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FIGURE 20: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

FIGURE 21: Data# Polling Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

FIGURE 22: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FIGURE 23: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FIGURE 24: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FIGURE 25: Block-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FIGURE 26: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

FIGURE 27: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

FIGURE 28: Software ID Exit (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FIGURE 29: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FIGURE 30: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FIGURE 31: Read Flowchart (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

FIGURE 32: Byte-Program Flowchart (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

FIGURE 33: Erase Command Sequences Flowchart (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

FIGURE 34: Software Product ID Command Sequences Flowchart (LPC Mode) . . . . . . . . . . . . . . . . . . . . 44

FIGURE 35: Byte-Program Command Sequences Flowchart (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 45

FIGURE 36: Wait Options Flowchart (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FIGURE 37: Software Product ID Command Sequences Flowchart (PP Mode) . . . . . . . . . . . . . . . . . . . . . 47

FIGURE 38: Erase Command Sequence Flowchart (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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3 Mbit / 4 Mbit / 8 Mbit LPC Flash

SST49LF030A / SST49LF040A / SST49LF080A

Advance Information

LIST OF TABLES

TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

TABLE 3: SST49LF030A / SST49LF040A Address bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TABLE 4: SST49LF080A Address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TABLE 5: Address Decoding Range for SST49LF030A / SST49LF040A . . . . . . . . . . . . . . . . . . . . . . . . . 13

TABLE 6: Address Decoding Range for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TABLE 7: LPC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TABLE 8: LPC Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TABLE 9: Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TABLE 10: General Purpose Inputs Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TABLE 11: Memory Map Register Addresses for SST49LF030A / SST49LF040A . . . . . . . . . . . . . . . . . . 18

TABLE 12: Memory Map Register Addresses for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TABLE 13: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TABLE 14: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

TABLE 15: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

TABLE 16: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

TABLE 17: Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

TABLE 18: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TABLE 19: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TABLE 20: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

TABLE 21: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

TABLE 22: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

TABLE 23: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TABLE 24: Read Cycle Timing Parameters (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TABLE 25: Program/Erase Cycle Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TABLE 26: Reset Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

S71206-01-000 1/02

554

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SST49LF040A-33-4C-NH Related Products

	SST49LF040A-33-4C-NH	SST49LF040A-33-4C-WH
Description	Flash, 512KX8, 11ns, PQCC32, PLASTIC, LCC-32	Flash, 512KX8, 11ns, PDSO32, 8 X 14 MM, TSOP1-32
Maker	Silicon Laboratories Inc	Silicon Laboratories Inc
Parts packaging code	QFJ	TSOP1
package instruction	QCCJ,	8 X 14 MM, TSOP1-32
Contacts	32	32
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
Maximum access time	11 ns	11 ns
Other features	120 NANO SECOND ACCESS TIME IN PARALLEL PROGRAMMING MODE	120 NANO SECOND ACCESS TIME IN PARALLEL PROGRAMMING MODE
JESD-30 code	R-PQCC-J32	R-PDSO-G32
length	13.97 mm	12.4 mm
memory density	4194304 bit	4194304 bit
Memory IC Type	FLASH	FLASH
memory width	8	8
Number of functions	1	1
Number of terminals	32	32
word count	524288 words	524288 words
character code	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
organize	512KX8	512KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	TSOP1
Package shape	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL
Programming voltage	3 V	3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.55 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal form	J BEND	GULL WING
Terminal pitch	1.27 mm	0.5 mm
Terminal location	QUAD	DUAL
width	11.43 mm	8 mm

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