FEDL228XX-05
Issue Date: Oct. 10, 2013
ML2282X-XXX/ML2286X-XXX
Speech Synthesis LSI with Built-in P2ROM Including 2-Channel Mixing Function
GENERAL DESCRIPTION
ML2282X(ML22825/ML22824/ML22823-XXX) and ML2286X (ML22865/ML22864/ML22863-XXX) are
voice synthesis LSIs with built-in P2ROM that stores speech data.
These LSIs include edit ROM, ADPCM2 decoder, 16-bit DA converter, low pass filter and monaural speaker
amplifier. Also, ML2282X supports the synchronous serial interface and ML22865/ML22864/ML22863
supports the I2C interface.
By integrating all the functions required for voice output into a single chip, these LSIs can be more easily
incorporated in compact portable devices.
•
Built-in memory capacity and maximum vocal reproduction time:
(at the case of 4-bit ADPCM2 algorithm)
Product name
ML22825-XXX/ML22865
ML22824-XXX/ML22864
ML22823-XXX/ML22863
ROM capacity
16 Mbits
8 Mbits
4 Mbits
Maximum vocal reproduction time (sec)
F
S
= 8.0 kHz
F
S
= 16 kHz
F
S
= 4.0 kHz
1,044
522
261
520
260
130
258
129
64
4-bit ADPCM2
8-bit Nonlinear PCM
8-bit PCM , 16-bit PCM
Can be specified for each phrase.
•
Sampling frequency(Fs):
4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 /
48.0 kHz
f
s
can be specified for each phrase.
•
Built-in low-pass filter and 16-bit DA converter
•
Speaker driving amplifier:
0.7 W (when 8Ω , DV
DD
=5 V, Ta=25°C)
2ch analog input (internal: 1ch; external: 1ch)
•
CPU command interface:
3-wired serial clock-synchronized (ML2282X)
I2C interface (ML2286X)
•
Maximum number of phrases:
4,096 phrases from 000h to 3FFh (1024 phrases/bank)
•
Memory bank switching:
Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins
•
Volume control:
32 levels (OFF is included) can be set by CVOL command.
50 levels (OFF is included) can be set by AVOL command
•
Repeat function:
LOOP commands
•
2-channel mixing function:
Available except case using 32kHz as sampling frequencys
•
Source oscillation frequency:
4.096 MHz
•
Power supply voltage:
2.7 to 3.6V / 4.5 to 5.5 V
•
Operating temperature range:
–40 to +85°C
•
Package:
30-pin plastic SSOP (SSOP30-P-56-0.65-K-MC)
•
Product name:
ML22825-xxxMB, ML22824-xxxMB, ML22823-xxxMB
ML22865-xxxMB, ML22864-xxxMB, ML22863-xxxMB
(xxx: ROM code No.)
•
Voice synthesis method:
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FEDL228XX-05
ML2282X-XXX/ ML2286X -XXX
The following table shows the differences among the other speech synthesis LSIs.
Parameter
CPU interface
Playback method
Maximum number
of phrases
Sampling
frequency (kHz)
ML2216
Serial
4-bit ADPCM2
8-bit nonlinear PCM
8-bit straight PCM
16-bit straight PCM
256
4.0/5.3/6.4/
8.0/10.6/12.8
16.0
4.096MHz
(with a built-in crystal
oscillator circuit)
12 bits
3rd order comb filter
Built-in 0.3W
(8Ω, DV
DD
= 5 V)
Yes
No
16 levels
Yes
20 ms to 1024 ms
(4 ms/step)
Yes
No
ML22800 series
←
←
ML22825/ML22824/
ML22823-XXX
←
←
ML22865/ML22864/
ML22863-XXX
I2C
←
1,024 (256/bank)
4,096 (1,024/bank)
4.0/5.3/6.4/8.0/
10.6/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0
←
16 bits
FIR interpolation filter
Built-in 0.7W
(8Ω, DV
DD
= 5 V)
←
2-channel
32 levels
←
←
←
←
←
←
Clock frequency
DA converter
Low-pass filter
Speaker driving
amplifier
Edit ROM function
Simultaneous
sound production
function (mixing
function)
Volume control
Silence insertion
Repeat function
Interval at which a
seam is silent
during continuous
playback (Note)
Memory bank
switching
Power supply
voltage
Package
←
12 bits
3rd order comb filter
No
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
No
2.7 V to 5.5 V
44-pin QFP
Yes
2.7 V to 3.6 V
30-pin SSOP
←
2.7 to 3.6V
4.5 to 5.5 V
←
←
2.7 to 3.6V
4.5 to 5.5 V
←
*1: Continuous playback as shown below is possible.
1 phrase
1 phrase
No silence interval
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FEDL228XX-05
ML2282X-XXX/ ML2286X -XXX
BLOCK DIAGRAMS
(ML22825/ML22824/ML22823-XXX : Synchronous serial interface)
DV
DD
DGND
V
DDL
V
DDR
Phrase Address
Latch
Address Counter
ADPCM Synthesizer
Address Controller
Multiplexer
16/8/4Mbit ROM
CSB
SCK
SI
SO
CBUSYB
DIPH
SEL0
SEL1
TESTI0,1
TESTO
RESETB
XT
XTB
PCM Synthesizer
I/O
Interface
LPF
Timing
Controller
16bit DAC
SP-AMP
OSC
PLL
SPV
DD
SPGND
SPM SPP
AIN
(ML22865/ML22864/ML22863-XXX : I2C interface)
DV
DD
DGND
V
DDL
V
DDR
Phrase Address
Latch
Address Counter
ADPCM Synthesizer
Address Controller
Multiplexer
16/8/4Mbit ROM
SDA2-0
SCL
SDA
CBUSYB
SEL0
SEL1
TESTI0,1
TESTO
RESETB
I/O
Interface
PCM Synthesizer
LPF
Timing
Controller
16bit DAC
XT
XTB
SP-AMP
OSC
PLL
SPV
DD
SPGND
SPM SPP
AIN
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FEDL228XX-05
ML2282X-XXX/ ML2286X -XXX
PIN CONFIGURATIONS (TOP VIEW)
(ML22825/ML22824/ML22823-XXXMB : Synchronous serial interface)
AIN
TESTI0
RESETB
TESTO
DIPH
SEL0
SEL1
DGND
CSB
SCK
SI
SO
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPV
DD
DGND
SG
TESTI1
V
DDR
DV
DD
V
DDL
NC
DGND
NC
DV
DD
XTB
NC: No Connection
30-Pin Plastic SSOP
(ML22865/ML22864/ML22863-XXXMB : I2C interface)
AIN
TESTI0
RESETB
TESTO
SAD0
SEL0
SEL1
DGND
SAD1
SCL
SDA
SAD2
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPV
DD
DGND
SG
TESTI1
V
DDR
DV
DD
V
DDL
NC
DGND
NC
DV
DD
XTB
NC: No Connection
30-Pin Plastic SSOP
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FEDL228XX-05
ML2282X-XXX/ ML2286X -XXX
PIN DESCRIPTION (COMMON TO ALL PRODUCTS)
Pin
1
2
Symbol
AIN
TESTI0
I/O
I
I
Initial value
Description
(*1)
0
Input pin for speaker amplifier.
Input pin for testing.
0
Fix this pin to “L” level (DGND level). This pin has a pull-down resistor
built in.
Input pin for reset.
At the “L” level, the LSI enters initial state. During reset, the entire
circuitry stops and enters power down state. Input “L” level when power is
0
supplied. After the power supply voltage is stable, drive this pin to “H”
(*2)
level. Then the entire circuitry can be powered up.
This pin has a pull-up resistor built in.
Output pins for testing.
Hi-Z
Leave these pins open.
Memory bank switching pins.
0
Fix these pins to “L” level when the memory bank function is not used.
—
1
Digital ground pin. Also serves as a ground pin for the internal memory.
Output pin for command processing status.
This pin outputs “L” level during command processing. Any command
should be entered when this pin is “H” level.
Connect to the crystal or ceramic resonator.
A feedback resistor around 1 MΩ is built in between this pin and the XTB
pin. Use this pin if need to use an external clock.
If the resonator is used, connect it as close to this pin as possible.
Connect to the crystal or ceramic resonator.
When to use an external clock, leave this pin open.
If the resonator is used, connect it as close to this pin as possible.
Power supply pins for logic circuitry.
Connect a capacitor of 0.1μF or more between these pins and DGND pins.
Non connected pins. Leave these pins open.
Regulator output pin for internal logic circuitry.
Connect a capacitor recommended between this pin and DGND pin.
Regulator output pin for Built-in ROM.
Connect a capacitor recommended between this pin and DGND pin.
Test pin. Fix this pin to a DGND level.
Reference voltage output pin for the speaker amplifier built-in.
Connect a capacitor recommended between this pin and DGND pin.
Power supply pin for the speaker amplifier.
Connect a bypass capacitor of 0.1μF or more between this pin and SPGND
pin.
Ground pin for the speaker amplifier.
Positive(+) output pin of the speaker amplifier built-in.
Serves as the LINE output (*3), if built-in speaker amplifier is not used.
Negative(-) output pin of the speaker amplifier built-in.
3
RESETB
I
4
6, 7
8, 14,
19, 26
13
TESTO
SEL0
SEL1
DGND
CBUSYB
O
I
—
O
15
XT
I
0
16
17, 22
18, 20
21
23
24
25
27
28
29
30
XTB
DV
DD
N.C
V
DDL
V
DDR
TESTI1
SG
SPV
DD
SPGND
SPP
SPM
O
—
—
—
—
—
—
—
—
O
O
1
—
—
0
0
0
0
—
—
0
Hi-Z
*1: Indicates the initial value during reset input or power down.
*2: “H” during power down.
*3: Outputs a voice signal before amplified by the speaker amplifier built-in.
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