DATASHEET
HIGH-PERFORMANCE 6-CHANNEL AC’97
2.3 CODEC WITH UNIVERSAL JACKS™
OVERVIEW
High performance, 6-channel, AC’97 2.3 CODECs with
high Signal-to-Noise ratio and low distortion.
STAC9758/9759
DESCRIPTION
IDT's STAC9758/9759 are general purpose 20-bit, full
duplex, 6-Channel audio CODECs conforming to the ana-
log component specification of AC '97 (Audio Codec 97
Component Specification Rev. 2.3). The STAC9758/9759
incorporates IDT's proprietary
Σ∆
technology to achieve a
DAC SNR in excess of 90dB. With IDT’s headphone drive
capability, headphones can be driven without an external
amplifier. The STAC9758/9759 communicates via the five
AC-Link to any digital component of AC '97, providing flexi-
bility in the audio system design. Packaged in an AC '97
compliant 48-pin TQFP, the STAC9758/9759 can be placed
on the motherboard, daughter boards, PCI, AMR, CNR,
MDC or ACR cards.
Supported ADC and DAC audio sample rates include
96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz,
11.025 kHz, and 8 kHz; additional rates are supported in
the STAC9758/9759 soft audio drivers. All ADCs and DACs
operate at 20-bit resolution. SPDIF_OUT supported sam-
ple rates include 96 kHz, 48 kHz, 44.1 kHz and 32 kHz.
SPDIF_IN supports 48 kHz and 44.1 kHz.
The STAC9758/9759 includes
internal
jack sensing using
proprietary IDT current and impedance-sensing tech-
niques. The impedance load on any of the inputs or outputs
can be detected. The STAC9758/9759 also supports
Uni-
versal Jacks
TM
functionality for jack interchangeability.
The GPIOs on the STAC9758/9759 remain available for
advanced configurations. The STAC9758/9759 can support
up to 5 GPIOs.
The STAC9758/9759 is designed primarily to support
6-channel audio. Additionally, the STAC9758/9759 pro-
vides for a stereo enhancement feature, IDT Surround 3D
(SS3D).
The STAC9758/9759 also supports the ADAT
®
Optical
“Litepipe” Interface, which provides an 8 channel output for
professional and consumer audio applications.
The STAC9758/9759 can be SoundBlaster
®
and Windows
Sound System
®
compatible when used with IDT’s WDM
driver for Windows 98/2K/ME/XP or with Intel/Microsoft
driver included with Windows 2K/ME/XP.
FEATURES
•
High performance
Σ∆
technology
•
6-Channel AC’97 2.3 CODECs
•
20-bit full duplex stereo ADCs
•
20-bit full duplex DACs
•
Headphone drive capability
•
SPDIF_IN Support
•
SPDIF_OUT Support, including 96 kHz
•
ADAT
®
Optical “Litepipe” Interface
Support
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Universal Jacks
TM
Functionality for jack
interchangeability
Internal
Jack Sensing
Crystal Elimination Circuit
Front/Rear Stereo Microphone
96 kHz DAC Playback support
Up to 5 General Purpose I/Os
Digital and Analog PC BEEP
AC’97 2.3 Paging Registers and Analog Plug and
Play Capability
Energy saving dynamic power modes
>90 dB SNR and >-90dBV THD+N
Adjustable VREF_OUT Control
Pin compatible with 2-Channel CODECs
Independent sample rates for ADC & DACs
+3.3 V & +5 V analog power supply options
SoundBlaster is a registered trademark of Creative Labs.
Windows is a registered trademark of Microsoft Corporation.
ADAT Optical is a registered trademark of Alesis Corporation.
IDT™
1
STAC9758/9759
V 1.1 101606
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
TABLE OF CONTENTS
1. DESCRIPTION ........................................................................................................................... 7
1.1. Features ........................................................................................................................................... 8
1.2. Block Diagram ................................................................................................................................... 9
2. CHARACTERISTICS/SPECIFICATIONS ................................................................................ 10
2.1. Electrical Specifications ................................................................................................................... 10
2.1.1. Absolute Maximum Ratings ............................................................................................... 10
2.1.2. Recommended Operation Conditions ............................................................................... 10
2.1.3. Power Consumption ......................................................................................................... 11
2.1.4. AC-Link Static Digital Specifications ................................................................................. 12
2.1.5. STAC9758 5V Analog Performance Characteristics ........................................................ 12
2.1.6. STAC9759 3.3V Analog Performance Characteristics ..................................................... 14
2.2. AC Timing Characteristics ............................................................................................................... 17
2.2.1. Cold Reset ......................................................................................................................... 17
2.2.2. Warm Reset ....................................................................................................................... 17
2.2.3. Clocks ................................................................................................................................ 18
2.2.4. STAC9758/9759 Crystal Elimination Circuit and Clock Frequencies ................................ 19
2.2.5. Data Setup and Hold ........................................................................................................ 20
2.2.6. Signal Rise and Fall Times ................................................................................................ 20
2.2.7. AC-Link Low Power Mode Timing ..................................................................................... 21
2.2.8. ATE Test Mode .................................................................................................................. 21
3. TYPICAL CONNECTION DIAGRAM ....................................................................................... 22
3.1. Split Independent Power Supply Operation .................................................................................... 23
4. CONTROLLER, CODEC AND AC-LINK ................................................................................. 25
4.1. AC-Link Physical interface ............................................................................................................... 25
4.2. Controller to Single CODEC ............................................................................................................ 25
4.3. Controller to Multiple CODECs ........................................................................................................ 27
4.3.1. Primary CODEC Addressing ............................................................................................. 27
4.3.2. Secondary CODEC Addressing ........................................................................................ 27
4.3.3. CODEC ID Strapping ......................................................................................................... 28
4.4. Clocking for Multiple CODEC Implementations ............................................................................... 28
4.5. STAC9758/9759 as a Primary CODEC ........................................................................................... 28
4.5.1. STAC9758/9759 as a Secondary CODEC ........................................................................ 28
4.6. AC-Link Power Management ........................................................................................................... 29
4.6.1. Powering down the AC-Link .............................................................................................. 29
4.6.2. Waking up the AC-Link ...................................................................................................... 29
4.6.3. CODEC Reset ................................................................................................................... 30
5. AC-LINK DIGITAL INTERFACE .............................................................................................. 31
5.1. Overview ......................................................................................................................................... 31
5.2. AC-Link Serial Interface Protocol .................................................................................................... 32
5.2.1. AC-Link Variable Sample Rate Operation ......................................................................... 33
5.2.2. Variable Sample Rate Signaling Protocol .......................................................................... 33
5.2.3. Primary and Secondary CODEC Register Addressing ...................................................... 34
5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 35
5.3.1. Slot 0: TAG / CODEC ID ................................................................................................... 36
5.3.2. Slot 1: Command Address Port ......................................................................................... 36
5.3.3. Slot 2: Command Data Port ............................................................................................... 37
5.3.4. Slot 3: PCM Playback Left Channel .................................................................................. 37
5.3.5. Slot 4: PCM Playback Right Channel ................................................................................ 37
5.3.6. Slot 5: Modem Line 1 Output Channel .............................................................................. 37
5.3.7. Slot 6 - 11: DAC ................................................................................................................. 37
5.3.8. Slot 12: Audio GPIO Control Channel ............................................................................... 38
5.4. AC-Link Input Frame (SDATA_IN) ................................................................................................. 38
5.4.1. Slot 0: TAG ........................................................................................................................ 39
IDT™
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STAC9758/9759
V 1.1 101606
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
5.4.2. Slot 2: Status Data Port ..................................................................................................... 40
5.4.3. Slot 3: PCM Record Left Channel ..................................................................................... 41
5.4.4. Slot 4: PCM Record Right Channel ................................................................................... 41
5.4.5. Slot 5: Modem Line 1 ADC ................................................................................................ 41
5.4.6. Slot 6-9: ADC ..................................................................................................................... 41
5.4.7. Slots 7-8: Vendor Reserved .............................................................................................. 41
5.4.8. Slot 10 & 11: ADC ............................................................................................................. 41
5.4.9. Slot 12: Reserved .............................................................................................................. 41
5.5. AC-Link Interoperability Requirements and Recommendations ...................................................... 42
5.5.1. “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data ............................................... 42
5.6. Slot Assignments for Audio ............................................................................................................. 42
6. STAC9758/9759 MIXER ......................................................................................................... 45
6.1. SPDIF Digital Mux ........................................................................................................................... 45
6.2.
SPDIF_IN .........................................................................................................................45
6.3. ADAT Optical “Lightpipe” Support ................................................................................................... 46
6.4. Digital PC Beep ............................................................................................................................... 46
6.5. Double Rate Audio .......................................................................................................................... 46
6.6. Double Rate SPDIF Output ............................................................................................................. 46
7. STAC9758/9759 MIXER DIAGRAM ........................................................................................ 47
8. PROGRAMMING REGISTERS ................................................................................................ 48
8.1. Program Register List ...................................................................................................................... 48
8.2. Program Register Descriptions ........................................................................................................ 50
8.2.1. Reset (00h) ........................................................................................................................ 50
8.2.2. Master Volume Registers (02h) ......................................................................................... 51
8.2.3. DAC-A Volume Register (04h) .......................................................................................... 52
8.2.4. Master Volume MONO (06h) ............................................................................................. 53
8.2.5. PC BEEP Volume (0Ah) .................................................................................................... 53
8.2.6. Digital PC Beep ................................................................................................................. 54
8.2.7. Phone Volume (0Ch) ......................................................................................................... 54
8.2.8. Mono/Stereo Mic Volume (0Eh) ........................................................................................ 56
8.2.9. Line In Volume (10h) ......................................................................................................... 58
8.2.10. CD Volume (12h) ............................................................................................................. 59
8.2.11. DAC-B to Mixer2 Volume Control (14h) ........................................................................... 60
8.2.12. Aux Volume (16h) ............................................................................................................ 62
8.2.13. PCMOut Volume (18h) .................................................................................................... 63
8.2.14. Record Select (1Ah) ........................................................................................................ 64
8.2.15. Record Gain (1Ch) .......................................................................................................... 65
8.2.16. General Purpose (20h) .................................................................................................... 66
8.2.17. 3D Control (22h) .............................................................................................................. 67
8.2.18. Audio Interrupt and Paging (24h) .................................................................................... 68
8.2.19. Powerdown Ctrl/Stat (26h) .............................................................................................. 70
8.2.20. Extended Audio ID (28h) ................................................................................................. 72
8.2.21. Extended Audio Control/Status (2Ah) .............................................................................. 74
8.3. PCM DAC Rate Registers ............................................................................................................... 76
8.3.1. PCM DAC Rate (2Ch) ....................................................................................................... 77
8.3.2. PCM Surround DAC Rate (2Eh) ........................................................................................ 77
8.3.3. PCM LFE DAC Rate (30h) ................................................................................................ 77
8.3.4. PCM LR ADC Rate (32h) .................................................................................................. 78
8.3.5. Center/LFE Volume (36h) .................................................................................................. 78
8.3.6. Surround Volume (38h) ..................................................................................................... 78
8.3.7. SPDIF Control (3Ah) .......................................................................................................... 79
8.4. General Purpose Input & Outputs ................................................................................................... 81
8.4.1. EAPD ................................................................................................................................. 81
8.4.2. GPIO Pin Definitions .......................................................................................................... 81
8.4.3. GPIO Pin Implementation .................................................................................................. 81
IDT™
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STAC9758/9759
V 1.1 101606
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
8.4.4. Extended Modem Status and Control Register (3Eh) ........................................................ 82
8.4.5. GPIO Pin Configuration Register (4Ch) ............................................................................. 82
8.4.6. GPIO Pin Polarity/Type Register (4Eh) ............................................................................. 83
8.4.7. GPIO Pin Sticky Register (50h) ......................................................................................... 83
8.4.8. GPIO Pin Mask Register (52h) .......................................................................................... 84
8.4.9. GPIO Pin Status Register (54h) ........................................................................................ 84
8.5. Extended CODEC Registers Page Structure Definition .................................................................. 85
8.5.1. Extended Registers Page 00 ............................................................................................. 85
8.5.2. Extended Registers Page 01 ............................................................................................. 85
8.5.3. Extended Registers Page 02, 03 ....................................................................................... 85
8.6. STAC9758/9759 Paging Registers ................................................................................................. 85
8.6.1. SPDIF_In Status 1 Register (60h,
Page 00h
) ..................................................................... 86
8.6.2. CODEC Class/Rev (60h
Page 01h
) .................................................................................... 86
8.6.3. SPDIF_In Status 2 Register (62h,
Page 00h
) ..................................................................... 87
8.6.4. PCI SVID (62h
Page 01h
) ................................................................................................... 88
8.6.5. Universal Jack
TM
Output Select (64h,
Page 00h
) ............................................................... 88
8.6.6. PCI SSID (64h
Page 01h
) ................................................................................................... 89
8.6.7. Universal Jack
TM
Input Select (66h,
Page 00h
) .................................................................. 90
8.6.8. Function Select (66h
Page 01h
) .......................................................................................... 91
8.6.9. I/O Misc. (68h,
Page 00h
) ................................................................................................... 92
8.6.10. Function Information (68h
Page 01h
) ................................................................................ 93
8.6.11. Digital Audio Control (6Ah,
Page 00h
) .............................................................................. 95
8.6.12. Sense Details (6Ah
Page 01h
) .......................................................................................... 96
8.6.13. Revision Code (6Ch,
Page 00h
) ........................................................................................ 97
8.6.14. DAC Slot Mapping (6Ch,
Page 01h
) ................................................................................. 97
8.6.15. Analog Special (6Eh,
Page 00h
) ....................................................................................... 98
8.6.16. ADC Slot Mapping (6Eh,
Page 01h
) ................................................................................ 100
8.6.17. IDT Reserved (70h) ....................................................................................................... 100
8.6.18. Various Functions (72h) ................................................................................................ 100
8.6.19. EAPD Access Register (74h) ........................................................................................ 102
8.6.20. Analog Misc. (76h) ......................................................................................................... 103
8.6.21. ADAT Control and HPF Bypass (78h) ........................................................................... 103
8.6.22. IDT Reserved Register (7Ah) ........................................................................................ 103
8.7. Vendor ID1 and ID2 (7Ch and 7Eh) .............................................................................................. 104
8.7.1. Vendor ID1 (7Ch) ............................................................................................................ 104
8.7.2. Vendor ID2 (7Eh) ............................................................................................................. 104
9. LOW POWER MODES ..........................................................................................................105
10. MULTIPLE CODEC SUPPORT ........................................................................................... 107
10.1. Primary/Secondary CODEC Selection ........................................................................................ 107
10.1.1. Primary CODEC Operation ........................................................................................... 107
10.1.2. Secondary CODEC Operation ....................................................................................... 107
10.2. Secondary CODEC Register Access Definitions ......................................................................... 108
11. TESTABILITY ...................................................................................................................... 109
11.1. ATE Test Mode ........................................................................................................................... 109
12. PIN DESCRIPTION .............................................................................................................. 110
12.1. Digital I/O ..................................................................................................................................... 110
12.2. Analog I/O ................................................................................................................................... 111
12.3. Filter/References ......................................................................................................................... 112
12.4. Power and Ground Signals ......................................................................................................... 112
13. ORDERING INFORMATION ................................................................................................ 113
14. PACKAGE DRAWING ......................................................................................................... 113
15. 48-PIN LQFP SOLDER REFLOW PROFILE ....................................................................... 114
15.1. Standard Reflow Profile Data ...................................................................................................... 114
15.2. Pb Free Process - Package Classification Reflow Temperatures ............................................... 115
IDT™
4
STAC9758/9759
V 1.1 101606
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
16. APPENDIX A: PROGRAMMING REGISTERS ...................................................................116
17. REVISION HISTORY ........................................................................................................... 118
LIST OF FIGURES
Figure 1. Cold Reset Timing .......................................................................................................................... 17
Figure 2. Warm Reset Timing ........................................................................................................................ 17
Figure 3. Clocks Timing ................................................................................................................................. 18
Figure 4. Data Setup and Hold Timing .......................................................................................................... 20
Figure 5. Signal Rise and Fall Times Timing ................................................................................................. 20
Figure 6. AC-Link Low Power Mode Timing .................................................................................................. 21
Figure 7. ATE Test Mode Timing ................................................................................................................... 21
Figure 8. Typical Connection Diagram .......................................................................................................... 22
Figure 9. Split Independent Power Supply Operation ................................................................................... 24
Figure 10. AC-Link to its Companion Controller ............................................................................................ 25
Figure 11. CODEC Clock Source Detection .................................................................................................. 26
Figure 12. STAC9758/9759 Powerdown Timing ........................................................................................... 29
Figure 13. Bi-directional AC-Link Frame with Slot assignments .................................................................. 31
Figure 14. AC-Link Audio Output Frame ....................................................................................................... 35
Figure 15. Start of an Audio Output Frame ................................................................................................... 35
Figure 16. STAC9758/9759 Audio Input Frame ........................................................................................... 38
Figure 17. Start of an Audio Input Frame ...................................................................................................... 38
Figure 18. Bi-directional AC-Link Frame with Slot Assignments ................................................................... 43
Figure 19. STAC9758/9759 Mixer Diagram .................................................................................................. 47
Figure 20. Example of STAC9758/9759 Powerdown/Powerup Flow .......................................................... 105
Figure 21. Powerdown/Powerup Flow With Analog Still Active .................................................................. 106
Figure 22. Pin Description Drawing ............................................................................................................. 110
Figure 23. Solder Reflow Profile ................................................................................................................. 114
IDT™
5
STAC9758/9759
V 1.1 101606
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
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