Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
V
CC
4.5V–5.5V
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature
3. Typical values are measured at V
CC
= 5V, T
A
= 25°C, and are included for reference only and are not tested or guaranteed.
Document #: 38-05039 Rev. *B
Page 2 of 11
CY62148B MoBL™
Electrical Characteristics
Over the Operating Range
CY62148B-70
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
Max. V
CC
,
CE
≥
V
IH
V
IN
≥
V
IH
or
V
IN
≤
V
IL
, f = f
MAX
Max. V
CC
,
CE
≥
V
CC
– 0.3V,
V
IN
≥
V
CC
– 0.3V,
or V
IN
≤
0.3V, f =0
Com/Ind’l
I
OUT
=0 mA
V
CC
= Max.,
Com/
Ind’l
Test Conditions
V
CC
= Min., I
OH
= – 1 mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
–0.3
–1
–1
12.5
2.5
1.5
Min.
2.4
0.4
V
CC
+0.3
0.8
+1
+1
20
Typ.
[3]
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB1
I
SB2
Com/
Ind’l
4
20
µA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
AC Test Loads and Waveforms
R1 1800
Ω
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
990
Ω
5V
OUTPUT
5 pF
R1 1800Ω
ALL INPUT PULSES
3.0V
90%
R2
990
Ω
GND
≤
3 ns
10%
90%
10%
≤
3 ns
(a)
INCLUDING
JIG AND
SCOPE
(b)
Equivalent to:
THEVENIN EQUIVALENT
639
Ω
1.77V
OUTPUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05039 Rev. *B
Page 3 of 11
CY62148B MoBL™
Switching Characteristics
[5]
Over the Operating Range
62148BLL-70
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
70
60
60
0
0
55
30
0
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
0
70
10
25
5
25
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05039 Rev. *B
Page 4 of 11
CY62148B MoBL™
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[9]
Description
V
CC
for Data Retention
Data Retention Current
Com’l
Ind’l
Operation Recovery Time
LL
LL
No input may exceed
V
CC
+ 0.3V
V
CC
= V
DR
= 3.0V
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
Min.
2.0
20
20
0
t
RC
Typ.
[3]
Max.
Unit
V
µA
µA
ns
ns
Chip Deselect to Data Retention Time
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No.1
[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[11, 12]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
HIGH
IMPEDANCE
DATA OUT
Notes:
9. Full Device operatin requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
µ
s or stable at V
cc(min)
> 100
µ
s.
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
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