AT45DB021B_14 datasheet, PDF - EEWORLD Datasheet

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AT45DB021B_14: DescriptionSerial Peripheral Interface (SPI) Compatible; File Size288KB，32 Pages; ManufacturerAtmel (Microchip)

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AT45DB021B_14 Overview

Serial Peripheral Interface (SPI) Compatible

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Features

•

Single 2.7V - 3.6V Supply

Serial Peripheral Interface (SPI) Compatible

20 MHz Max Clock Frequency

Page Program Operation

– Single Cycle Reprogram (Erase and Program)

– 1024 Pages (264 Bytes/Page) Main Memory

Supports Page and Block Erase Operations

Two 264-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming of Nonvolatile Memory

Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

Low Power Dissipation

– 4 mA Active Read Current Typical

– 2 µA CMOS Standby Current Typical

Hardware Data Protection Feature

100% Compatible to AT45DB021 and AT45DB021A

5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins

Commercial and Industrial Temperature Ranges

Green (Pb/Halide-free/RoHS Compliant) Packaging Options

•

2-megabit

2.7-volt Only

DataFlash

AT45DB021B

•

1. Description

The AT45DB021B is a 2.7-volt only, serial interface Flash memory ideally suited for

a wide variety of digital voice-, image-, program code- and data-storage applications.

Its 2,162,688 bits of memory are organized as 1024 pages of 264 bytes each. In addi-

tion to the main memory, the AT45DB021B also contains two SRAM data buffers

of 264 bytes each. The buffers allow receiving of data while a page in the main mem-

ory is being reprogrammed, as well as reading or writing a continuous data stream.

EEPROM emulation (bit or byte alterability) is easily handled with a self-

contained three step Read-Modify-Write operation. Unlike conventional Flash

memories that are accessed randomly with multiple address lines and a parallel inter-

face, the DataFlash uses a SPI serial interface to sequentially access its data.

DataFlash supports SPI mode 0 and mode 3. The simple serial interface facilitates

hardware layout, increases system reliability, minimizes switching noise, and reduces

package size and active pin count. The device is optimized for use in many commer-

cial and industrial applications where high density, low pin count, low voltage, and low

power are essential. The device operates at clock frequencies up to 20 MHz with a

typical active read current consumption of 4 mA.

To allow for simple in-system reprogrammability, the AT45DB021B does not require

high input voltages for programming. The device operates from a single power supply,

2.7V to 3.6V, for both the program and read operations. The AT45DB021B is enabled

through the chip select pin (CS) and accessed via a three-wire interface consisting of

the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming cycles are self-timed, and no separate erase cycle is required before

programming.

When the device is shipped from Atmel, the most significant page of the memory

array may not be erased. In other words, the contents of the last page may not be

filled with FFH.

1937J–DFLSH–9/05

5. Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions

and their associated opcodes are contained in Tables 1 through 4 (pages

and

11).

A valid

instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the

desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin

controls the loading of the opcode and the desired buffer or main memory address location

through the SI (serial input) pin. All instructions, addresses, and data are transferred with the

most significant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 to denote

the nine address bits required to designate a byte address within a buffer. Main memory

addressing is referenced using the terminology PA9 - PA0 and BA8 - BA0 where PA9 - PA0

denotes the 10 address bits required to designate a page address and BA8-BA0 denotes the

nine address bits required to designate a byte address within the page.

5.1

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either

one of the two data buffers. The DataFlash supports two categories of read modes in relation to

the SCK signal. The differences between the modes are in respect to the inactive state of the

SCK signal as well as which clock cycle data will begin to be output. The two categories, which

are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock

Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to

Table 5-3 on page 9

for a complete list) is used to select which category will be used for reading. Please refer to the

“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle

sequences for each mode.

5.1.1

Continuous Array Read

By supplying an initial starting address for the main memory array, the Continuous Array Read

command can be utilized to sequentially read a continuous stream of data from the device by

simply providing a clock signal; no additional addressing information or control signals need to

be provided. The DataFlash incorporates an internal address counter that will automatically

increment on every clock cycle, allowing one continuous read operation without the need of

additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be

clocked into the device followed by 24 address bits and 32 don’t care bits. The first five bits of

the 24-bit address sequence are reserved for upward and downward compatibility to larger and

smaller density devices (see Notes under “Command Sequence for Read/Write Operations” dia-

gram). The next 10 address bits (PA9- PA0) specify which page of the main memory array to

read, and the last nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte

address within the page. The 32 don’t care bits that follow the 24 address bits are needed to ini-

tialize the read operation. Following the 32 don’t care bits, additional clock pulses on the SCK

pin will result in serial data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bits, the don’t care

bits, and the reading of data. When the end of a page in main memory is reached during a Con-

tinuous Array Read, the device will continue reading at the beginning of the next page with no

delays incurred during the page boundary crossover (the crossover from the end of one page to

the beginning of the next page). When the last bit in the main memory array has been read, the

device will continue reading back at the beginning of the first page of memory. As with crossing

over page boundaries, no delays will be incurred when wrapping around from the end of the

array to the beginning of the array.

AT45DB021B

1937J–DFLSH–9/05

AT45DB021B

A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.

The maximum SCK frequency allowable for the Continuous Array Read is defined by the f

CAR

specification. The Continuous Array Read bypasses both data buffers and leaves the contents

of the buffers unchanged.

5.1.2

Main Memory Page Read

A Main Memory Page Read allows the user to read data directly from any one of the 1024 pages

in the main memory, bypassing both of the data buffers and leaving the contents of the buffers

unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device fol-

lowed by 24 address bits and 32 don’t care bits. The first five bits of the 24-bit address sequence

are reserved bits, the next 10 address bits (PA9-PA0) specify the page address, and the next

nine address bits (BA8- BA0) specify the starting byte address within the page. The 32 don’t

care bits which follow the 24 address bits are sent to initialize the read operation. Following the

32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial

output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the

don’t care bits and the reading of data. When the end of a page in main memory is reached dur-

ing a Main Memory Page Read, the device will continue reading at the beginning of the same

page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the

SO pin.

Buffer Read

Data can be read from either one of the two buffers, using different opcodes to specify which

buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode

of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the

opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t care bits. Since

the buffer size is 264-bytes, nine address bits (BFA8-BFA0) are required to specify the first byte

of data to be read from the buffer. The CS pin must remain low during the loading of the opcode,

the address bits, the don’t care bits and the reading of data. When the end of a buffer is reached,

the device will continue reading back at the beginning of the buffer. A low-to-high transition on

the CS pin will terminate the read operation and tri-state the SO pin.

5.1.4

Status Register Read

The status register can be used to determine the device’s ready/busy status, the result of a Main

Memory Page to Buffer Compare operation, or the device density. To read the status register,

an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is

shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on

the SO pin during the next eight clock cycles. The five most-significant bits of the status register

will contain device information, while the remaining three least-significant bits are reserved for

future use and will have undefined values. After bit 0 of the status register has been shifted out,

the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting

again with bit 7. The data in the status register is constantly updated, so each repeating

sequence will output new data.

Table 5-1.

Bit 7

RDY/BUSY

5.1.3

Status Register Format

Bit 6

COMP

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is

not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy

state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level

1937J–DFLSH–9/05

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