Highly-Integrated, Fully-Featured 6-port DS3/E3/STS-1
Jitter-Attenuator and STS-1 to DS3/E3 Desynchronizer
M 2 8 3 2 6 Digital Jitter-Attenuator (DJAT)
Mindspeed Technologies™ offers its first
6-port DS3/E3/STS-1 Jitter-Attenuator and
desynchronizer based on DJAT technology
Mindspeed’s DJAT technology performs critical jitter-
attenuation and signal desynchronization functions to
improve performance and reliability in both telecommun-
ciations and data communications equipment surrounding
the edge of the optical network.
>
K E Y F E AT U R E S
>
High density: up to 12 inde-
>
One second timer for event
pendent jitter-attenuators and
latching
desynchronizers for DS3/E3,
>
Ability to dejitter AMI or
and STS-1 in one package
NRZ input data
>
Low power: <250 mW maximum
>
Ability to independently bypass
power consumption
the JAT for each channel
>
Programmable FIFO depth
>
Power-down control for each
optimal for SONET/SDH
channel
>
Crystal-less jitter-attenuation
>
Small 15 mm BGA package
>
Programmable clocking of both
>
Single 3.3 V supply
inputs and outputs on either edge
>
Two PRBS generator/detector
per channel
This high density, low power solution is designed for
transmission applications including add/drop multiplexers,
routers, ATM multi-service switches, digital cross connects,
and DS3 to STS-1 mappers. The M28326 6-port DJAT
device can be combined with Line Interface Units (LIUs)
and mapper devices in addressing traffic-aggregation
equipment needs in converting high-speed Synchronous
Transport Signal-1 (STS-1) streams to asynchronous
lower-speed DS3/E3 data rates for systems used in data
centers and points of presence (POPs).
frames, generating a network compliant clock. The M28326
6-port DJAT seamlessly interfaces with Mindspeed’s
DS3/E3/STS-1 LIU devices — M28331/2/3 (1/2/3-port),
M28335 (12-port), and CX28365 (12-port DS3/E3 framer
with ATM TC) — providing a complete solution for high
The 12-port M28326 DJAT leverages Mindspeed’s advance
digital signal processing techniques along, with extensive
knowledge of analog mixed signal design, that provide the
first solution of its kind to adapt and fully smooth a STS-1
clock (with overhead gaps) to a network compliant DS3 or
E3 line clock.
density DS3/E3 line cards.
Jitter Definition
Jitter is defined as the short-term variations of the
significant instants of any signal from their ideal position
in time. The short-term variations are phase oscillations
of the digital signal. Clock jitter can lead to incorrect
The M28326 6-port DJAT complies with Telcordia GR-253
and GR-499, ETSI TBR-24, ANSI T1.105.03b, as well as ITU
G.751, G.755, G.783, and G.823 standards. For Category I
interfaces, the M28320 12-port DJAT device smooths the
inherent jitter due to demapping, bit stuffing and pointer
adjustments in DS3 or E3 payloads extracted from STS-1
data bit sampling, resulting in bit errors.
Jitter can be caused by any or all of the following:
– Interference
– Oscillator phase noise
– Signal distortion
– Stuffing jitter
– Demapping jitter
– Pointer jitter
>
Jitter-Attenuator and Desynchronizer
Jitter-attenuator (JAT) smooths the phase differences of clock
signals due to phase variations between STRATUM clocks, bit
stuffing, pointer adjustments due to frequency differences, and
demapping of STS-1 payloads. There are two modes of operation for
the M28326 6-port DJAT. The first involves attenuating jitter from
a clock signal of E3, DS3, or STS-1 data rates. This is typically
referred to as a Category II interface. Clock jitter on this interface
is also referred to as line timing jitter. The second mode of opera-
tion, for a Category I interface, involves extracting an E3 or DS3
payload from a STS-1 frame. Clock jitter on this interface is also
referred to as demapping jitter.
Microprocessor Interface
In hardware mode, the M28326 6-port device requires little or
no control and may be statically configured. The M28326 6-port
device also supports a 4 signal serial and a parallel 8-bit micro-
processor interface that allows access to extended features such
as the PRBS generators and bit error rate (BER) counters. Control
and status registers are memory mapped.
M28326
DIN_P(0)
DIN_N(0)
WCLK (0)
PRBS
(Gen/Det)
FIFO &
Phase Detector
PRBS
(Gen/Det)
DOUT_P(0)
DOUT_N(0)
RCLK (0)
REFCLK(0)
JAT 0
JAT 5
Timing Control &
PLL
Control
MODE0
MODE1
SCCLK
IN_SMP
OUT_SMP
JAT_MODE
PAD_OE
DS3MODE
Functional Block Diagram
Product Features
• High density: up to 6 independent
jitter-attenuators and desynchro-
nizers for DS3/E3,and STS-1 in one
package
• Low power: <250 mW maximum
power consumption
• Programmable FIFO depth optimal
for SONET/SDH
• Crystal-less jitter-attenuation
• Programmable clocking of both
inputs and outputs on either edge
• Two PRBS generator/detector per
channel
• One second timer for event latching
• Ability to dejitter AMI or NRZ
input data
• Ability to independently bypass the
JAT for each channel
• Power-down control for each channel
• Small 15 mm BGA package
• Single 3.3 V supply
OE
WR
ADDR(AA,8:0)
DATA(7:0)
E3
JAT_EN(5:0)
PD(5:0)
SCLK
SDIN
SDOUT
CS
RESET
INT
Applications
•
Digital Cross-connect systems
•
Multi-service ATM switches
•
Routers
•
Add/drop Multiplexers
www.mindspeed.com/salesoffices
General Information: (949) 579-3000
Headquarters – Newport Beach
4000 MacArthur Blvd., East Tower
Newport Beach, CA 92660-3007
Order# 500295A M01-0638
© 2002 Mindspeed Technologies
™
, a Conexant business. All rights reserved. Mindspeed
and the Mindspeed logo are trademarks of Mindspeed Technologies. All other
trademarks are the property of their respective owners. Although Mindspeed
Technologies strives for accuracy in all its publications, this material may contain
errors or omissions and is subject to change without notice.
This material is provided
as is and without any express or implied warranties, including merchantability, fitness
for a particular purpose and non-infringement.
Mindspeed Technologies shall not be
liable for any special, indirect, incidental or consequential damages as a result of its use.
京公网安备 11010802033920号
EEWORLD
