V436616R24V(L)
128 MB 168-PIN UNBUFFERED DIMM
3.3 VOLT 16M x 64 LOW PROFILE
PRELIMINARY
CILETIV LESOM
Features
Component Used
t
CK
t
AC
Description
The V436616R24V(L) memory module is
organized 16, 777, 216 x 64 bits in a 168 pin dual in
line memory module (DIMM). The 16M x 64
memory module uses 4 Mosel-Vitelic 16M x 16
SDRAM. The x64 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.
s
168 Pin Unbuffered 16, 777, 216 x 64 bit
Oganization SDRAM DIMM
s
Utilizes High Performance 256 Mbit, 16M x 16
SDRAM in TSOPII-54 Packages
s
Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
s
Single +3.3V (± 0.3V) Power Supply
s
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
s
Auto Refresh (CBR) and Self Refresh
s
All Inputs, Outputs are LVTTL Compatible
s
8192 Refresh Cycles every 64 ms
s
Serial Present Detect (SPD)
s
SDRAM Performance
-7
CL=3
CL=2
Clock Access Time CAS CL=3
Latency
CL=2
143
100
5.4
6
Units
MHz
MHz
ns
ns
Clock Frequency (max.)
s
Supported Latencies at 133 MHz Operation for
Module
CL
3
t
RCD
3
t
RP
3
t
RC
8
CLK
V436616R24V(L) Rev. 1.0 November 2001
1
V436616R24V(L)
CILETIV LESOM
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin Configurations (Front Side/Back Side)
Front
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Notes:
*
These pins are not used in this module.
Pin Names
A0–A12
I/O1–I/O64
RAS
CAS
WE
BA0, BA1
CKE0, CKE1
CS0–CS3
CLK0–CLK3
DQM0–DQM7
VCC
VSS
SCL
SDA
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Bank Selects
Clock Enable
Chip Select
Clock Input
Data Mask
Power (+3.3 Volts)
Ground
Clock for Presence Detect
Serial Data OUT for Presence
Detect
SA0–A2
CB0–CB7
NC
DU
Serial Data IN for Presence
Detect
Check Bits (x72 Organization)
No Connection
Don’t Use
V436616R24V(L) Rev. 1.0 November 2001
2
V436616R24V(L)
CILETIV LESOM
V
MOSEL VITELIC
MANUFACTURED
SDRAM
Part Number Information
4
3
66
16
R
2
4
V
A
T
G - XX
(L)
3.3V
WIDTH
DEPTH
168 PIN Unbuffered
DIMM X16 COMPONENT
REFRESH
RATE 8K
SPEED
75PC = PC133 CL3,2
75 = PC133 CL3
10PC = PC133 CL3,2
LEAD FINISH
G = GOLD
COMPONENT
PACKAGE, T = TSOP
COMPONENT
REV LEVEL
LVTTL
4 BANKS
LOW RPROFILE
Part Number
V436616R24VATG-75L
V436616R24VATG-10PCL
Description
128 MB, 16M x 64, 133 MHz, CL3
128 MB, 16M x 64, 100 MHz, CL2
Functional Block Diagram
10
CLK1/3
3.3pF
WE
CS0
WE
LDQM
I/O1–I/O8
10
DQM1
I/O9–I/O16
10
CS2
DQM2
I/O17–I/O24
10
DQM3
I/O25–I/O32
10
UDQM
I/O9–I/O16
DQM7
I/O57–I/O64
10
CKE0
RAS
CAS
WP
47K
CS
DQM4
I/O33–I/O40
10
DQM5
I/O41–I/O48
10
DQM0
I/O1–I/O8
WE
LDQM
I/O1–I/O8
UDQM
I/O9–I/O16
CS
UDQM
I/O9–I/O16
D0
D2
WE
LDQM
I/O1–I/O8
CS
DQM6
I/O49–I/O56
10
WE
LDQM
I/O1–I/O8
UDQM
I/O9–I/O16
CS
D1
D3
E
2
PROM SPD (256 WORD X 8 BITS)
SCL0
SA2
SA1
SA0
SDA
CKE: SDRAM D0–D3
RAS: SDRAM D0–D3
CAS: SDRAM D0–D3
WE: SDRAM D0–D3
A(12:0): SDRAM D0–D3
BA0, BA1: SDRAM D0–D3
D0–D3
C0–C7
D0–D3
Two 0.1µF capacitors
per each SDRAM
WE
A(12:0)
BA0, BA1
V
CC
10
D0/D2
D1/D3
CLK0/2
3.3pF
V
SS
V436616R24V(L) Rev.1.0 November 2001
3
V436616R24V(L)
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
A serial presence detect storage device -
2
PROM - is assembled onto the module. Informa-
E
tion about the module configuration, speed, etc. is
CILETIV LESOM
SPD-Table:
Byte Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Serial Presence Detect Information
Hex Value
Function Described
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x16 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back Random
Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active Delay t
RRD
Minimum RAS to CAS Delay t
RCD
Minimum RAS Pulse Width t
RAS
SPD Entry Value
128
256
SDRAM
13
9
1
64
0
LVTTL
7.5 ns
5.4 ns
none
Self-Refresh, 7.8µs
x16
n/a / x16
t
ccd
= 1 CLK
1, 2, 4, 8
4
CL =2, 3
CS Latency = 0
WL = 0
Non Buffered/Non Reg.
Vcc tol ± 10%
10.0 ns
6.0 ns
Not Supported
Not Supported
20 ns
15 ns
20 ns
45 ns
16Mx64
80
08
04
0D
09
01
40
00
01
75
54
00
82
10
00
01
0F
04
06
01
01
00
0E
A0
60
00
00
14
0F
14
2D
V436616R24V(L) Rev. 1.0 November 2001
4
V436616R24V(L)
CILETIV LESOM
Byte Number
31
32
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Reserved
SPD-Table: (Continued)
Hex Value
Function Described
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
00
64
8D
00
V436616R24V(L)
Mosel Vitelic
Revision 2.0
SPD Entry Value
128 MByte
1.5 ns
0.8 ns
1.5 ns
0.8 ns
16Mx64
20
15
08
15
08
00
02
29
40
00
Intel Specification for Frequency
Supported Features
Unused Storage Location
DC Characteristics
T
A
= 0°C to 70°C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
Limit Values
Symbol
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (I
OUT
= –2.0 mA)
Output Low Voltage (I
OUT
= 2.0 mA)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
Min.
2.0
–0.5
2.4
—
–40
Max.
V
CC
+0.3
0.8
—
0.4
40
Unit
V
V
V
V
µA
µA
–40
40
V436616R24V(L) Rev.1.0 November 2001
5
京公网安备 11010802033920号
EEWORLD
