IT8702F
Super – Low Pin Count Input / Output
(LPC I/O)
Preliminary Specification V0.5
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please
contact sales representatives.
Copyright
©
2004 ITE Tech. Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related
products included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to
ITE’s Standard Terms and Conditions, a copy of which is included in the back of this document.
All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT8702F is a trademark of ITE Tech. Inc.
Intel is claimed as a trademark by Intel Corp.
Microsoft and Windows are claimed as trademarks by Microsoft Corporation.
PCI is claimed as a trademark by the PCI Special Interest Group.
IrDA is claimed as a trademark by the Infrared Data Association.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE Tech. Inc.
Marketing Department
8F, No. 233-1, Bao Chiao RD., Hsin Tien,
Taipei County 231, Taiwan, R.O.C.
Phone:
Fax:
(02) 29126889
(02) 2910-2551, 2910-2552
If you have any marketing or sales questions, please contact:
P.Y. Chang,
at ITE Taiwan: E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052,
Fax: 886-2-29102551
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
Or e-mail
itesupport@ite.com.tw
for more product information/services
Revision History
Revision History
Section
4
5
5
5
6
6
6
6
11
Added a PCIRST5# function.
Added ATXPG pin and revised the PWROK circuit to add two AND
inputs, SUSB# and ATXPG.
Added 2 extra sets FAN_TAC4, 5 and FAN_CTL4, 5.
Changed the pad types of MCLK, MDAT, KCLK and KDATA from
DIOD16 to DIOD24.
Changed the chip version register from 06h to 07h.
Added a PWROK1/2 delay time selection register for option.
Changed the default value of the pin multi-function selection of pin-84.
Changed the default value of FAN_CTL’s PWM clock into 22~27Khz.
Figure 11-12 was revised.
Revision
Page No.
7, 8
19
7, 8, 10, 11
18
34
35
38
75
153
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IT8702F V0.5
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