Ordering number : EN*A1811A
CMOS IC
LE24CBK222
Overview
Triple port EEPROM
Two Wire Serial Interface
(2K+2K EEPROM)
The triple port EEPROM series consists of two independent banks, and each bank can be controlled separately using
dedicated control pins. The EEPROM also features a control port, which is a third pin separate from the pins used for the
banks, and by accessing the memory areas from this control port, the two-bank configuration (2K bits + 2K bits) can be
used as a pseudo-one-bank configuration (4K bits). Together with the 16-byte page write function, this enables a
reduction in the number of factory write processes.
Furthermore, the EEPROM has a configuration area which is separate from the 2K-bit + 2K-bit area, and by using the
settings stored in this configuration area, it is possible to change the slave address for each port and to set read/write
protection for each port.
This product incorporates SANYO's high performance CMOS EEPROM technology and realizes high-speed operation
and high-level reliability. The interface of this product is compatible with the I
2
C bus protocol, making it ideal as a
nonvolatile memory for small-scale parameter storage.
In addition, this product also supports DDC2
TM
, so it can also be used as an EDID data storage memory for display
equipment.
Functions
: Bank1:2K bits (256
×
8 bits) + Bank2:2K bits (256
×
8 bits)
+ configuration area: 128 bits (16
×
8 bits), 4224 bits in total
•
Single supply voltage
: 2.5V to 5.5V
•
Interface
: Two wire serial interface (I
2
C Bus*), VESA DDC2
TM
compliant** 3-port access
•
Operating clock frequency : 400kHz (max)
•
Low power consumption : Standby: 5μA (max)
: One-bank read: 0.5 mA (max.), Two-bank simultaneous read: 1.0 mA (max.)
* : I C Bus is a trademark of Philips Corporation.
** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer
'
s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
'
s products or
equipment.
2
•
Capacity
Continued on next page.
10511 SY/92910 SY No.1811-1/20
LE24CBK222
Block Diagram
VDD
Port 1
SDA1
SCL1
Port 2
SDA2
SCL2
Low VCC
Detect
State
Control
Bank1
(2k EEPROM)
IO Buffer
Port
Control
IO Buffer
Control Port
SDAC
SCLC
Port
Control
Port
Control
Bank2
(2k EEPROM)
IO Buffer
Configuration Area
Protect info.
Slave Address
Slave Enable
Description of Operation
Access to Bank1 is performed through port 1 (SCL1 / SDA1), and access to Bank2 through port 2 (SCL2 / SDA2).
When read operations are performed, Bank1 and Bank2 can be controlled independently of each other and both banks
can be accessed at the same time. When write operations are performed, it is not possible to access both banks while a
write operation is in progress in one of the banks (including the write wait time).
Both Bank1 and Bank2 can be accessed from the control port (SCLC, SDAC). The two-bank configuration (2K bits +
2K bits) can be used as a pseudo-one-bank configuration (4K bits). Data correlation is guaranteed between the mode in
which accesses are made from port1 or port 2 and the mode in which accesses are made from the control port, enabling
operations such as writing data from control port in a lump and reading data from port 1 or port 2.
Access to the configuration area where the slave addresses of the ports and protect information is stored is made from
the control port.
Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
DC input voltage
Over-shoot voltage
Storage temperature
Tstg
Below 20ns
Symbol
Conditions
Ratings
-0.5 to +6.5
-0.5 to +5.5
-1.0 to +6.5
-65 to +150
Unit
V
V
V
°C
Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Operating Conditions
Parameter
Operating supply voltage
Operating temperature
Symbol
Conditions
Ratings
2.5 to 5.5
-40 to +85
Unit
V
°C
No.1811-3/20
LE24CBK222
DC Electrical Characteristics
Parameter
Supply current at reading
(when either Bank1 or Bank2 is read)
Supply current at reading
(when both Bank1 and Bank2 are read
simultaneously)
Supply current at writing
Standby current
Input leakage current
Output leakage current (SDA)
Input low voltage
Input high voltage
ICC2
ISB
ILI
ILO
VIL
VIH
VOL
Output low level voltage
IOL=0.7mA, VDD=2.5V
IOL=3.0mA, VDD=2.5V
IOL=3.0mA, VDD=5.5V
IOL=6.0mA, VDD=4.5V
VDD*0.7
0.2
0.4
0.4
0.6
f=400kHz, tWC=5ms
VIN=VDD or GND
VIN=GND to VDD
VOUT=GND to VDD
-2.0
-2.0
0.7
5
5
+2.0
+2.0
VDD*0.3
mA
μA
μA
μA
V
V
V
V
V
V
ICC12
f=400kHz
1.0
mA
Symbol
ICC11
f=400kHz
Conditions
min
VDD=2.5V to 5.5V
typ
max
0.5
mA
Unit
Capacitance/Ta=25°C,
f=100kHz
Parameter
In/Output capacitance
Input capacitance
Symbol
CI/O
CI
Conditions
VI/O=0V (SDA1, SDA2, SDAC)
VIN=0V (SCL1, SCL2, SCLC)
min
typ
2
2
max
5
5
Unit
pF
pF
Note: This parameter is sampled and not 100% tested.
AC Electric Characteristics
Fast Mode
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL, SDA rise time
SCL, SDA fall time
Bus release time
Noise suppression time
Write cycle time
Symbol
min
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
1200
100
5
1200
600
100
100
600
600
100
0
600
300
300
900
VDD=2.5V to 5.5V
typ
max
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
unit
No.1811-4/20
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EEWORLD
