VF2510BGILF datasheet, PDF - EEWORLD Datasheet

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VF2510BGILF: DescriptionTSSOP-24, Tube; Categorylogic logic; File Size101KB，7 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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TSSOP-24, Tube

VF2510BGILF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	24
Manufacturer packaging code	PGG24
Reach Compliance Code	compliant
ECCN code	EAR99
series	2510
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G24
JESD-609 code	e3
length	7.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	24
Actual output times	10
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	3.7 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.1 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

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Integrated

Circuit

Systems, Inc.

ICSVF2510

3.3V Phase-Lock Loop Clock Driver

General Description

The ICSVF2510

is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology to

align, in both phase and frequency, the CLKIN signal with

the CLKOUT signal. It is specifically designed for use with

synchronous SDRAMs. The

ICSVF2510

operates at 3.3V

VCC and drives up to ten clock loads.

One bank of ten outputs provide low-skew, low-jitter

copies of CLKIN. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLKIN.

Outputs can be enabled or disabled via control (OE)

inputs. When the OE inputs are high, the outputs align in

phase and frequency with CLKIN; when the OE inputs are

low, the outputs are disabled to the logic low state.

The

ICSVF2510

does not require external RC filter

components. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost. The

test mode shuts off the PLL and connects the input

directly to the output buffer. This test mode, the

ICSVF2510

can be use as low skew fanout clock buffer device. The

ICSVF2510

comes in 24 pin 173mil Thin Shrink Small-

Outline package (TSSOP) package.

Features

•

Meets or exceeds PC133 registered DIMM

specification1.1

Spread Spectrum Clock Compatible

Distributes one clock input to one bank of ten outputs

Operating frequency 20MHz to 200MHz

External feedback input (FBIN) terminal is used to

synchrionize the outputs to the clock input

No external RC network required

Operates at 3.3V Vcc

Plastic 24-pin 173mil TSSOP package

Block Diagram

FBOUT

CLK0

CLK1

CLK2

FBIN

CLKIN

PLL

CLK3

CLK4

AVCC

CLK5

CLK6

CLK7

CLK8

CLK9

Pin Configuration

AGND

VCC

CLK0

CLK1

CLK2

GND

CLK3

CLK4

VCC

FBOUT

CLKIN

AVCC

VCC

CLK9

CLK8

GND

CLK7

CLK6

CLK5

VCC

FBIN

24 Pin TSSOP

4.40 mm. Body, 0.65 mm. Pitch

0722A—05/07/03

ICSVF2510

VF2510BGILF Related Products

	VF2510BGILF	VF2510BGILFT	VF2510BGT	VF2510BG	VF2510BGLF	VF2510BGLFT
Description	TSSOP-24, Tube	TSSOP-24, Reel	TSSOP-24, Reel	TSSOP-24, Tube	TSSOP-24, Tube	TSSOP-24, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Contains lead	Contains lead	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	incompatible	incompatible	conform to	conform to
Parts packaging code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
package instruction	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,
Contacts	24	24	24	24	24	24
Manufacturer packaging code	PGG24	PGG24	PG24	PG24	PGG24	PGG24
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
series	2510	2510	2510	2510	2510	2510
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e3	e3	e0	e0	e3	e3
length	7.8 mm	7.8 mm	7.8 mm	7.8 mm	7.8 mm	7.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	1	1	1	1	1
Number of functions	1	1	1	1	1	1
Number of terminals	24	24	24	24	24	24
Actual output times	10	10	10	10	10	10
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260	240	240	260	260
propagation delay (tpd)	3.7 ns	3.7 ns	3.7 ns	3.7 ns	3.7 ns	3.7 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.1 ns	0.1 ns	0.1 ns	0.1 ns	0.1 ns	0.1 ns
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V
Minimum supply voltage (Vsup)	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	MATTE TIN	TIN LEAD	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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