IDT71V67902S85BGGI datasheet, PDF

Datasheet> All Categories > storage> storage> IDT71V67902S85BGGI

IDT71V67902S85BGGI: DescriptionCache SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119; Categorystorage storage; File Size985KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

IDT71V67902S85BGGI Overview

Cache SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V67902S85BGGI Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	8.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	CACHE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm

Preview

Download Datasheet

View All

256K X 36, 512K X 18

IDT71V67702

3.3V Synchronous SRAMs

IDT71V67902

2.5V I/O, Burst Counter

Flow-Through Outputs, Single Cycle Deselect

Features

256K x 36, 512K x 18 memory configurations

Supports fast access times:

– 7.5ns up to 117MHz clock frequency

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW byte write

GW),

enable (BWE and byte writes (BW

BWE),

BWx)

BWE

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O supply (V

DDQ

)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA).

Description

The IDT71V67702/7902 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V67702/7902 SRAMs contain write,

data, address and control registers. There are no registers in the data

output path (flow-through architecture). Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V67702/7902 can provide four cycles of

data for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V67702/7902 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5317 tbl 01

NOTE:

and

are not applicable for the IDT71V67902.

DECEMBER 2003

DSC-5317/08

Recommended Resources

Single pulse signal generating circuit c

Operation circuit of frequency converter with braking unit and motor with brake

Northern brand BD-90 refrigerator circuit

Level converter composed of IC

Linear voltage to frequency converter circuit

Cable TV supplementary channel receiving circuit

TTI and Molex live broadcast at 10 am today | Smaller, faster, more reliable connectors drive new developments in IoT applications: Live Details: Smaller, faster, more reliable connectors drive new developments in IoT applicationsLive broadcast time: July 31, 2019 (today) 10:00-11:30 amLive Topic: Smaller, faster, and more reliabl...; EEWORLD社区 Integrated technical exchanges

MSP430 Timer Parameters: 1.1 Basic timertypedef enum { TIMER_A0 , TIMER_A1 , TIMER_A2 , TIMER_B0 , TIMER_NUM , }TIMERn; //Timer module1.2 Timer channel pin, clock selectionconst GPIO_PIN TIMER_CHANEL_PIN [TIMER_NUM][TIMER_CH_...; Aguilera Microcontroller MCU

What are the Wireless Power Consortium standards and TI compatible solutions?: Wireless charging technology shows great potential in the consumer market. Charging electronic devices without the use of wires not only provides a convenient solution for portable device users, but a...; qwqwqw2088 Wireless Connectivity

PWM output of MPS430 microcontroller: 2.2 PWM output2.2.1 PWM counting mode#define TIMER_MC_STOP (0) /* Timer A mode control: 0 - Stop */#define TIMER_MC_UP (1) /* Timer A mode control: 1 - Up to CCR0 */#define TIMER_MC_CONTINUOUS (2) /* ...; Aguilera Microcontroller MCU

PCB Design Considerations: 1. Confirmation of the board frame diagram (provided by the structural engineer). Design can only start after the board frame diagram is OK . After the PCB design is completed, the structure needs to ...; bandy PCB Design

LD array driver power supply with temperature adaptive regulation: Traditional drive power supplies usually adopt the working mode of current parameter preset input, which can only output the drive current of given pulse width, repetition frequency and peak value. Th...; zbz0529 Power technology

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components