QL82SD-4PB516I datasheet, PDF - EEWORLD Datasheet

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QL82SD-4PB516I: DescriptionField Programmable Gate Array, 2016 CLBs, 536000 Gates, CMOS, PBGA516, 1.27 MM PITCH, PLASTIC, BGA-516; CategoryProgrammable logic devices Programmable logic; File Size4MB，60 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL82SD-4PB516I Overview

Field Programmable Gate Array, 2016 CLBs, 536000 Gates, CMOS, PBGA516, 1.27 MM PITCH, PLASTIC, BGA-516

QL82SD-4PB516I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	BGA
package instruction	BGA,
Contacts	516
Reach Compliance Code	compliant
Combined latency of CLB-Max	0.555 ns
JESD-30 code	S-PBGA-B516
length	35 mm
Humidity sensitivity level	3
Configurable number of logic blocks	2016
Equivalent number of gates	536000
Number of terminals	516
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2016 CLBS, 536000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.52 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	35 mm

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QL82SD Device Data Sheet

••••••

Device Highlights

LVDS SERDES Basic Features

•

10 High Speed Bus LVDS Serial Links—

•

Extended Features

The following can be implemented into the

programmable logic:

•

UTOPIA Level 2, 16-bit wide System

•

bandwidth up to 5 Gbps

Eight Independent Bus LVDS serial

transceivers with operating speeds to 632

Mbps per channel

Two Independent Bus LVDS clock serial

transceivers with operating speeds to

400 MHz per channel

Integrated clock and data recovery (CDR)

with no external analog components

required

CDR bypass for applications with external

clock source

Programmable serial to parallel

configuration

10-bit data width—with

clock recovery

4-bit, 7-bit and 8-bit data widths—

with external clock

1-bit asynchronous level conversion

Fast Lock and Random (auto) Lock capable

Lock signal feedback

I/O support for LVTTL, LVCMOS, PCI,

GTL+, SSTL2, SSTL3, LVDS, LVPECL

Low Power/Independent power-down

mode for each SERDES channel

IEEE1149.1 JTAG Support &

boundary scan

Operation over PCB or backplane traces, or

across twisted pair cabling up to 25 m

Point-to-Point, Multi-Point, and Multi-Drop

Support

Pre-Emphasis Control on each LVDS

Channel Link

•

interface (up to 50 MHz) with parity support

for ATM applications

UTOPIA Level 3 compatible 8-bit wide

system Interface (up to 100 MHz) with parity

support for ATM applications

CSIX-L1 32-bit switch fabric interface (up to

100 MHz)

Supports Generic 8,16,32-bit

microprocessor bus interface for

configuration, control and status monitoring

Supports Generic 32, 64-bit peripheral bus

interface for bridging functions

Flexible Programmable Logic

•

2,016 Programmable Logic Cells

•

536 K System Gates

•

Muxed architecture; non-volatile technology

•

Completely customizable for any digital

application

Dual Port SRAM Blocks

•

36 Dual Port SRAM Blocks

•

Configurable array sizes (by 2, 4, 9, 18)

•

< 3 ns access times, FIFO capable of over

300 MHz

•

Configurable as RAM or FIFO

Preliminary

www.quicklogic.com

•

QL82SD Device Data Sheet Rev C

LVDS SERDES Applications

The QuickSD device is designed to address the need for high-speed serial communications.

It maintains the features of standard discrete SERDES devices, but integrates these features

with customizable logic to allow for the highest degree of flexibility, performance, and

integration at the lowest cost. The QuickSD device is designed to support both transmit and

receive requirements in a single chip. The device can support multiple channels in a variety

of modes (with or without clock recovery,) a variety of translation widths (1:1 to 1:10), as

well as a range of frequencies. These capabilities make this device ideal in applications where

the performance is critical and customization is required.

The QuickSD device targets three applications: on-board, board-to-board (via common

backplane), and box-to-box (via common cable).

Software Support

The turnkey QuickWorks



package from QuickLogic



provides the most complete ESP and

FPGA software solution from design entry to logic synthesis, to place and route, and to

simulation. The package provides a solution for designers who use third-party tools from

Cadence, Mentor, OrCAD, Synopsys, Viewlogic, Veribest and other third-party tools for

design entry, synthesis, or simulation. A power calculator is also provided for SERDES power

consumption.

To speed up the QuickSD design process, QuickLogic includes a SERDES Wizard in its

QuickWorks package. This wizard simplifies the process of configuring the multi-channel

SERDES core into each of its modes. For details on the SERDES Wizard, please refer to "The

QL82SD Quickstart Design Guide". To find this guide go to the QuickSD device

documentation Web page at

htt p: //www.qui ck logi c.co m/ho me . asp?Pag eID =31 5&sMenuI D=1 99#Order

Process Data

QuickSD is fabricated on a 0.25

µ,

five-layer metal CMOS process. The core voltage is

2.5 Volt V

supply and 3.3 V tolerant I/O with the addition of 3.3 Volt V

CCIO

. QuickSD is

available in commercial and industrial temperature grades.

•

www.quicklogic.com

•

Preliminary

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