TB6572AFG
TOSHIBA Bi- CMOS Integrated Circuit
Silicon Monolithic
TB6572AFG
3-Phase Full-Wave Brushless Motor Controller
Featuring Speed Control and Sine Wave PWM Drive
The TB6572AFG is a 3-phase full-wave brushless motor
controller IC that employs a sine wave PWM drive mechanism
with a speed control function.
Sine wave current driving with 2-phase modulation enables the
IC to drive a motor with high efficiency and low noise.
It also incorporates a speed control circuit that can vary the
motor speed using to an external clock.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Sine wave PWM drive
2-phase modulation with low switching loss
Triangular wave generator
Dead time function
External clock input
Speed discrimination
+PLL
speed control circuit
Ready circuit output
FG amplifier
Automatic lead angle correction
Forward/stop/reverse/brake functions
Current limiter
Lock protection
Weight: 0.50 g (typ.)
This product has a MOS structure and is sensitive to electrostatic discharge. When handling this product, ensure that
the environment is protected against electrostatic discharge by using an earth strap, a conductive mat and an ionizer.
Ensure also that the ambient temperature and relative humidity are maintained at reasonable levels.
Pin with low withstand voltage: pin 33
Do not insert devices in the wrong orientation or incorrectly. Otherwise, it may cause the device breakdown, damage
and/or deterioration.
The TB6572AFG is a RoHS-compatible.
About solderability, following conditions were confirmed:
•
Solderability
(1) Use of Sn-37Pb solder Bath
· solder bath temperature
=
230°C
· dipping time
=
5 seconds
· the number of times
=
once
· use of R-type flux
(2) Use of Sn-3.0Ag-0.5Cu solder Bath
· solder bath temperature
=
245°C
· dipping time
=
5 seconds
· the number of times
=
once
· use of R-type flux
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2008-1-21
TB6572AFG
Block Diagram
C20
R19
R17
R16
L3
L2
11
C17
R15
L4
29
C14
R14
C15
S-GND
19
25
Td2
24
Td1
36
VCC
C19 VCO-C
R18
C18
Fref
LP1
16
18 17
C12 C13
24 V
Vref2
L1
26
C16
VDD
31
27 28
VCO-R
Vref1(5 V)
R1
C21
HA+
Phase comparator
LPF
VCO
Automatic
Idc
lead angle
correction
A/D 5 bit
5V
Triangular
wave
generator
8V
Internal
reference
33
C11
51
1/1024 frequency
divider
CP1
38
HA−
52
C22 HB+
1
HB− 2
C23 HC+
6 bit (fx/252)
Charge
pump
37
C10
CP2
39
CP3
42
Output
waveform
C9
R20
R21
R22
Nch
+
Nch
R23
R24
R25
M
Position
estimation
Counter
Data
selector
120/180
Predriver
LA(U)
LB(U)
LC(U)
3
HC− 4
R2
R3
13
45
48
Ready
circuit
Gain
LP1
Control
switching
Frequency
&
gate
PWM
Ha/Hb/Hc
Fref
CW/CCW
120°
energization
matrix
Dead
time
setting
44
LA(L)
LB(L)
LC(L)
Ready
Speed
discriminator
block
Predriver
47
PLL
SEL_1
14
SEL_2
15
50
Protection
&
reset
－
+
43
OUT-A
Lock
protection
t
Vcc
READY
V
CC
Bounce
Prevention
5V
46
OUT-B
49
OUT-C
P-out
D-out_
R4
22
23
21
20
5
FGin+
R5 C1 R6
INTEG-in
6 FGin−
R9
R8
C5
7
FGO
12
8
10
9
40
41
30
CLd
FGS
R10
CW START
BRAKE
/CCW
5V
Idc2
Idc1
C6
Vref1
34
35
Vref1-R
P-GND
32
R12
C7
R13
C8
Vcc
R11
INTEG-out
C2
C3
R7 C4
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TB6572AFG
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Name
HB+
HB−
HC+
HC−
FGin+
FGin−
FGo
CW/CCW
BRAKE
START
Fref
FGS
Ready
SEL1
SEL2
LP1
VCO-R
VCO-C
S-GND
Pin Functions
Phase-B hall signal input
+
pin
Phase-B hall signal input
−
pin
Phase-C hall signal input
+
pin
Phase-C hall signal input
−
pin
FG amplifier input
+
pin
FG amplifier input
−
pin
FG amplifier output pin
Forward/reverse switching pin
Brake
Start
External clock input
FG hysteresis comparator output pin
Ready output pin
Gain Select 1
Gain Select 2
For LPF
Resistor pin for VCO
Capacitor pin for VCO
Ground pin
Pull-up resistor: 50 kΩ (typ.),H: Reverse/L: Forward
Pull-up resistor: 50 kΩ (typ.), L for braking
(all-phase ON for lower circuit)
Pull-up resistor: 50 kΩ (typ.), L for start, H for standby
Pull-up resistor: 50 kΩ (typ.)
Open collector output, I
O
=
1 mA (max)
Open collector output
Within
±6%:
L, Otherwise: High impedance
Selectable from four values. 25-kΩ pull-up resistor (typ.)
Selectable from four values. 25-kΩ pull-up resistor (typ.)
PLL form an external clock
A resistor should be added between this pin and ground.
A capacitor should be added between this pin and ground.
Remarks
Input the positive phase-B Hall device signal.
Input the negative phase-B Hall device signal.
Input the positive phase-C Hall device signal.
Input the negative phase-C Hall device signal.
FG signal input
FG signal input
INTEG-out Integral amp output
INTEG-in
D-out
P-out
Td1
Td2
L1
L2
L3
L4
CLd
VDD
P-GND
Vref2
Vref1
Vref1-R
VCC
CP2
Integral amp input
Speed discriminator deviation output
Phase deviation output
Frequency setting pin 1 for internal
reference clock
Frequency setting pin 2 for internal
reference clock
Lead angle correction circuit
Lead angle correction circuit
Lead angle correction circuit
Lead angle correction circuit
Oscillation pin for lock protection circuit
Internal logic power supply pin
Ground pin
8-V reference power supply
5-V reference power supply
5-V reference power supply
Voltage input pin for control power supply
Charge pump pin
8-V output. A capacitor should be added between this pin
and ground.
5-V output. A capacitor should be added between this pin
and ground.
A resistor should be added between VCC and Vref1-R.
V
CC
(opr.)
=
10 to 28 V
For generating upper N-ch FET gate voltage
Connect external CR to generate a reference clock.
Connect external CR to generate a reference clock.
Connect an external capacitor.
Connect an external resistor for adjusting the correction
gain.
Connect an external resistor for adjusting the correction
gain.
Connect an external capacitor
A capacitor should be added between this pin and ground
5-V output. A capacitor should be added between this pin
and ground.
Negative pin
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2008-1-21
TB6572AFG
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name
CP1
CP3
Idc2
Idc1
LA (U)
OUT-A
LA (L)
LB (U)
OUT-B
LB (L)
LC (U)
OUT-C
LC (L)
HA+
HA−
Pin Functions
Charge pump pin
Charge pump pin
Input pin for output current detection signal
Input pin for output current detection signal
Phase-A energization signal output (U1)
Phase-A motor pin
Phase-A energization signal output (L)
Phase-B energization signal output (U)
Phase-B motor pin
Phase-B energization signal output (L)
Phase-C energization signal output (U)
Phase-C motor pin
Phase-C energization signal output (L)
Phase-A hall signal input
+
pin
Phase-A hall signal input
−
pin
For phase-C output FET gate (lower N-ch)
Input the positive phase-A Hall device signal.
Input the negative phase-A Hall device signal.
For phase-B output FET gate (lower N-ch)
For source driving for phase-C output FET gate (upper N-ch)
For phase-A output FET gate (lower N-ch)
For phase-B output FET gate (upper N-ch)
Remarks
For generating upper N-ch FET gate voltage
For generating upper N-ch FET gate voltage
GND sense pin
Gate block operation when 0.25 V (typ.) or higher
For source driving for phase-A output FET gate (upper N-ch)
Pin Layout
Vref1-R
P-GND
Vref1
Vref2
VDD
CP3
CP1
CP2
CLd
Vcc
L4
L3
39
Idc2
Idc1
LA(U)
OUT-A
LA(L)
LB(U)
OUT-B
LB(L)
LC(U)
OUT-C
LC(L)
HA+
HA-
40
41
42
43
44
45
46
47
48
49
50
51
52
1
HB+
38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
2
HB-
3
HC+
4
HC-
5
FGin+
6
FGin-
7
FGo
8
CW/CCW
9
BRAKE
10 11 12 13
START
FGS
Ready
Fref
L1
Td2
Td1
P-out
D-out
INTEG-in
INTEG-out
S-GND
VCO-C
VCO-R
LP1
SEL2
SEL1
*:
Device destruction caused by electrical shorts between adjacent pins
If pins 36 and 37, pins 37 and 38, or pins 39 and 40 are shorted together, the device may be permanently damaged,
causing excessive current to flow, and consequently, smoke may result. To prevent overcurrent conditions or
excessive current in case of an IC failure, an appropriate power supply fuse should be used. To minimize its effect,
its capacitance and fusing time need to be adjusted.
L2
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2008-1-21
TB6572AFG
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristics
Supply voltage
Input voltage
Symbol
V
CC
V
IN
Rating
30 (Note 1)
5.5 (Note 2)
5.5 (Note 3)
Output voltage
V
OUT
30 (Note 4)
40 (Note 5)
10 (Note 6)
Output current
V
OUT
20 (Note 7)
25 (Note 8)
Power dissipation
Operating temperature
Storage temperature
P
D
T
opr
T
stg
1.3 (Note 9)
−30
to 85
−55
to 150
W
°C
°C
mA
V
Unit
V
V
Note 1: V
CC
Note 2: CW/CCW, START, BRAKE, Idc2, F
ref
, SEL1, SEL2,
Note 3: Ready, FGS
Note 4: OUT-A, OUT-B, OUT-C
Note 5: LA (U), LB (U), LC (U)
Note 6: Source current capability for LA (U), LB (U), LC (U), LA(L), LB(L), LC (L)
Note 7: Sink current capability for LA (U), LB (U), LC (U), LA(L), LB(L), LC (L)
Note 8: V
ref1
Note 9: When mounted on the board
(glass epoxy, 50 mm
×
50 mm
×
1.6 mm, copper foil 36%, thickness
=
18
μm,
single-sided)
The absolute maximum ratings are the limits that must not be exceeded, even for a moment, under worst possible
conditions.
Exceeding the ratings may cause device breakdown, damage or deterioration, and may also lead to breakdown,
damage or deterioration in other devices. This possibility should be fully considered in the design of the board.
The TB6572AFG should be operated within the specified operating range.
Operating Conditions
(Ta
=
25°C)
Characteristics
Supply voltage
External clock frequency
Symbol
V
CC
F
ref
Rating
10 to 28
200 to 4000
Unit
V
Hz
*: The maximum F
ref
value should be no greater than four times the minimum F
ref
value.
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2008-1-21
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