EEWORLDEEWORLDEEWORLD

Part Number

Search

GS8160ZV18AT-333T

Description
ZBT SRAM, 1MX18, 4.7ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size490KB,23 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS8160ZV18AT-333T Overview

ZBT SRAM, 1MX18, 4.7ns, CMOS, PQFP100, TQFP-100

GS8160ZV18AT-333T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time4.7 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeR-PQFP-G100
length20 mm
memory density18874368 bit
Memory IC TypeZBT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX18
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)2 V
Minimum supply voltage (Vsup)1.6 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Preliminary
GS8160ZV18/36AT-350/333/300/250/200/150
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
350 MHz–150 MHz
1.8 V V
DD
1.8 V I/O
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160ZV18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8160ZV18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Functional Description
The GS8160ZV18/36AT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
Parameter Synopsis
-350
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
1.8
2.85
395
455
4.5
4.5
270
305
-333
2.0
3.0
370
430
4.7
4.7
250
285
-300
2.2
3.3
335
390
5.0
5.0
230
270
-250
2.3
4.0
280
330
5.5
5.5
210
240
-200
2.7
5.0
230
270
6.5
6.5
185
205
-150
3.3
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow
Through
2-1-1-1
Rev: 1.00a 6/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/23
© 2003, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号