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WMS512K8V-17FECA

Description
Standard SRAM, 512KX8, 17ns, CMOS, CDFP32, CERAMIC, FP-32
Categorystorage    storage   
File Size107KB,9 Pages
ManufacturerWhite Electronic Designs Corporation
Websitehttp://www.wedc.com/
Download Datasheet Parametric View All

WMS512K8V-17FECA Overview

Standard SRAM, 512KX8, 17ns, CMOS, CDFP32, CERAMIC, FP-32

WMS512K8V-17FECA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerWhite Electronic Designs Corporation
package instructionCERAMIC, FP-32
Reach Compliance Codeunknown
Maximum access time17 ns
I/O typeCOMMON
JESD-30 codeR-CDFP-F32
length20.83 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL32,.4
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum seat height2.777 mm
Maximum standby current0.015 A
Minimum standby current3 V
Maximum slew rate0.15 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.41 mm
WMS512K8V-XXX
HI-RELIABILITY PRODUCT
512Kx8 MONOLITHIC SRAM
FEATURES
s
Access Times 15, 17, 20ns
s
Revolutionary, Center Power/Ground Pinout
JEDEC Approved
• 36 lead Ceramic SOJ (Package 100)
• 36 lead Ceramic Flat Pack (Package 226)
s
Evolutionary, Corner Power/Ground Pinout
JEDEC Approved
• 32 pin Ceramic DIP (Package 300)
• 32 lead Ceramic SOJ (Package 101)**
• 32 lead Ceramic Flat Pack (Package 220)**
s
32 pin, Rectangular Ceramic Leadless Chip Carrier
(Package 601)
PRELIMINARY*
s
Low Power CMOS
s
Low Voltage Operation:
• 3.3V
±
10% Power Supply
s
Commercial, Industrial and Military Temperature Range
s
TTL Compatible Inputs and Outputs
s
Fully Static Operation:
• No clock or refresh required.
s
Three State Output.
* This data sheet describes a product that is not fully qualified or
characterized and is subject to change without notice.
** Package under developement.
REVOLUTIONARY PINOUT
36 FLAT PACK
36 CSOJ
EVOLUTIONARY PINOUT
32 DIP
32 CSOJ (DE)**
32 FLAT PACK (FE)**
32 CLCC
TOP VIEW
A0
A1
A2
A3
A4
CS
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
TOP VIEW
A12
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
TOP VIEW
A14
A16
A18
V
CC
A15
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
V
SS
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
Power Supply
Ground
April 2001 Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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