Programmable LVCMOS/LVTTL
Clock Generator
IDT5V925BI
DATA SHEET
General Description
The IDT5V925BI is a high-performance, low skew, low jitter
phase-locked loop (PLL) clock driver. It provides precise phase and
frequency alignment of its clock outputs to an externally applied
clock input or internal crystal oscillator. The IDT5V925BI has been
specially designed to interface with Gigabit Ethernet and Fast
Ethernet applications by providing a 125MHz clock from 25MHz
input. It can also be programmed to provide output frequencies
ranging from 3.125MHz to 160MHz with input frequencies ranging
from 3.125MHz to 80MHz.
The IDT5V925BI includes an internal RC filter that provides
excellent jitter characteristics and eliminates the need for external
components. When using the optional crystal input, the chip accepts
a 10-30MHz fundamental mode crystal with a maximum equivalent
series resistance of 50
. The on-chip crystal oscillator includes the
feedback resistor and crystal capacitors (nominal load capacitance
is 18pF).
Features
•
•
•
•
•
•
•
•
•
•
•
•
3V to 3.6V operating voltage
3.125MHz to 160MHz output frequency range
Four programmable frequency LVCMOS/LVTTL outputs
Input from fundamental crystal oscillator or external source
Balanced drive outputs ±12mA
PLL disable mode for low frequency testing
Select inputs (S[1:0]) for divide selection (multiply ratio of 2, 3, 4,
5, 6, 7 and 8)
5V tolerant inputs
Low output skew/jitter
External PLL feedback, internal loop filter
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Pin Assignment
Applications
•
•
•
•
•
Ethernet/fast ethernet
Router
Network switches
SAN
Instrumentation
S
1
S
0
GNDQ
V
DDQ
X
1
X
2
CLKIN
FB
1
2
3
4
5
6
7
8
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
V
DD
GND
Q
2
Q
1
Q
0
Q/N
GND
OE
IDT5V925BI
16 LEAD QSOP
0.194” x 0.236” x 0.058” package body
Q Package
Top View
S0
S1
Block Diagram
SELECT
MODE
FB
CLKIN
PHASE
DETECTOR
LOOP
FILTER
VCO
0
1
X2
VCO
DIVIDE
1/N
Q/N
Q0
XTAL
OSC
X1
OPTIONAL
CRYSTAL
Q1
Q2
OE
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2
3
4
5
6
7
8
9
10, 15
11
12, 13, 14
16
Name
S1, S0
GNDQ
V
DDQ
X1
(1)
X2
(1)
CLKIN
FB
OE
GND
Q/N
Q0, Q1, Q2
V
DD
Input
Power
Power
Input
Output
Input
Input
Input
Power
Output
Output
Power
Type
Pullup/
Pulldown
Description
Three level divider/mode select pins. Float to MID.
Ground supply for PLL.
Power supply for PLL.
Crystal oscillator input. Connected to GND if oscillator not required.
Crystal oscillator output. Leave unconnected for clock input.
Clock input.
PLL feedback input which should be connected to Q/N output pin only. PLL locks
onto positive edge of FB signal.
High-Impedance output enable. When asserted HIGH, clock outputs are high
impedance.
Ground supply for output buffers.
Programmable divide-by-N clock output.
Output at N*CLKIN frequency.
Power supply for output buffers.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
NOTE 1: For best accuracy, use parallel resonant crystal specified for a load capacitance of 18pF.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.3V±0.3V
Test Conditions
CLKIN, FB, OE
V
DD
= 3.6V
Minimum
Typical
4
15
47
47
16
Maximum
Units
pF
pF
k
k
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Function Tables
Table 3A. Function Table
Allowable CLKIN Range (MHz)
(1, 2)
Output Used for Feedback
Q/N
Minimum
25/N
Maximum
160/N
Output Frequency Relationships
Q/N
CLKIN
Q[2:0]
CLKIN x N
NOTE 1: Operation in the specified CLKIN frequency range guarantees that the VCO will operate in the optimal range of 25MHz to 160MHz.
Operation with CLKIN outside specified frequency ranges may result in invalid or out-of-lock outputs.
NOTE 2: Q[2:0] are not allowed to be used as feedback.
Table 3B. Divide Selection Table
(1)
S1
L
L
L
M
M
M
H
H
H
S0
L
M
H
L
M
H
L
M
H
2
3
4
5
(3)
(default)
6
7
8
16
Divide-by-N Value
Factory Test
(2)
PLL
PLL
PLL
PLL
PLL
PLL
PLL
TEST
(4)
Mode
NOTE 1: H = HIGH, M = MEDIUM, L = LOW.
NOTE 2: Factory Test Mode: operation not specified.
NOTE 3: Ethernet mode (use a 25MHz input frequency and Q/N as feedback).
NOTE 4: Test mode for low frequency testing. In this mode, CLKIN bypasses the VCO (VCO powered down). Frequency must be > 1MHz due
to dynamic circuits in the frequency dividers. Q[2:0] outputs are divided by 2 in test mode.
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage to Ground, V
TERM
DC Input Voltage, V
IN
DC Output Voltage, V
OUT
Maximum Power Dissipation, T
A
= 85C
Storage Temperature, T
STG
Package Thermal Impedance,
JA
Rating
-0.5V to +4.6V
-0.5V to +4.6V
-0.5 to V
DD
+0.5V
0.55W
-65C to +150C
72.3C/W
Operating Conditions
Symbol
V
DD
/ V
DDQ
T
A
Description
Power Supply Voltage
Operating Temperature
Minimum
3.0
-40
Typical
3.3
+25
Maximum
3.6
+85
Units
V
C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
I
DDQ
Parameter
Quiescent Supply Current
Test Conditions
V
DD
= V
DDQ
= 3.6V; CLKIN = 2.5MHz;
S[1:0] = MM, OE = H,
All Outputs Unloaded
V
DD
= V
DDQ
= 3.6V;
S[1:0] = MM, OE = H,
All Outputs Unloaded
V
DD
= V
DDQ
= 3.6V, f
OUT
= 70MHz;
S[1:0] = LM, OE = GND,
All Outputs Loaded with 50 to GND
Minimum
Typical
2
Maximum
4
Units
mA
Static Supply Current
I
DD
Dynamic Supply Current
83
102
mA
80
160
mA
NOTE: H = HIGH, M = MEDIUM, L = LOW
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Table 4B. LVCMOS/LVTTL DC Characteristics
,
V
DD
= 3.3V ± 0.3V,
T
A
= -40°C to 85°C
Symbol
V
IL
V
IH
V
IHH
V
IMM
V
ILL(1)
I
IN(1)
I
3(1)
I
IH
V
OL
V
OH
Parameter
Input Low Voltage
Input High Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Leakage Current
3-Level Input
DC Current
Input High Current
Output Low Voltage
Output High Voltage
S[1:0]
S[1:0]
S[1:0]
CLKIN, FB
3-Level Input Only
3-Level Input Only
3-Level Input Only
V
IN
= V
DD
or GND, V
DD
= Max.
V
IN
= V
DD,
HIGH Level
S[1:0]
V
IN
= V
DD
/2
,
MID Level
V
IN
= GND, LOW Level
V
IN
= V
DD
I
OL
= 12mA
I
OH
= -12mA
2.4
-50
-200
-5
0.07
0.15
2.8
±5
0.55
-5
2
V
DD
- 0.6
V
DD
/2 - 0.3
V
DD
/2 + 0.3
0.6
+5
200
+50
Test Conditions
Minimum
Typical
Maximum
0.8
Units
V
V
V
V
V
µA
µA
µA
µA
µA
V
V
NOTE: Conditions apply unless otherwise specified.
NOTE 1: These inputs are normally wired to V
DD,
GND, or unconnected. If the inputs are switched in real time, the function and timing of the
outputs may glitch, and the PLL may require an additional lock time before all the datasheet limits are achieved.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
10
Test Conditions
Minimum
Typical
Fundamental
30
50
7
MHz
Maximum
Units
pF
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
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