K4S283233E-F(H)E/N/G/C/L/F
1M x 32Bit x 4 Banks SDRAM in 90FBGA
FEATURES
•
•
•
•
3.0V & 3.3V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
EMRS cycle with address key programs.
-. PASR(Partial Array Self Refresh)
-. Internal TCSR(Temperature Compensated Self Refresh)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
Extended Temperature Operation (-25
°C
~ 85°C).
Commercial Temperature Operation (-25
°C
~ 70
°C).
90Balls Monolithic FBGA(9mm x 13mm)
Pb for -FXXX, Pb Free for -HXXX.
Mobile-SDRAM
GENERAL DESCRIPTION
The K4S283233E is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth and
high performance memory system applications.
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ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S283233E-F(H)E/N/G/C/L/F60 166MHz(CL=3)
133MHz(CL=3)
90FBGA
105MHz(CL=2) LVCMOS
Pb
K4S283233E-F(H)E/N/G/C/L/F1H 105MHz(CL=2)
(Pb Free)
K4S283233E-F(H)E/N/G/C/L/F75
K4S283233E-F(H)E/N/G/C/L/F1L 105MHz(CL=3)
*1
- F(H)E/N/G : Normal/Low Power, Extended Temp.
- F(H)C/L/F : Normal/Low Power, Commercial Temp.
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
1M x 32
1M x 32
1M x 32
1M x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
May. 2003
K4S283233E-F(H)E/N/G/C/L/F
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
9
A
e
B
C
D
D
E
F
G
D
1
H
J
K
D/2
L
M
N
P
R
E
E/2
8
7
6
5
4
3
2
1
Mobile-SDRAM
< Top View
*2
>
90Ball(6x15) CSP
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
V
SSQ
V
SSQ
V
DDQ
V
SS
A4
A7
CLK
DQM1
V
DDQ
V
SSQ
V
SSQ
DQ11
DQ13
2
DQ24
V
DDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DDQ
DQ15
3
V
SS
V
SSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
V
SS
DQ9
DQ14
V
SSQ
V
SS
7
V
D D
V
DDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
V
D D
DQ6
DQ1
V
DDQ
V
D D
8
DQ23
V
SSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
V
SSQ
DQ0
9
DQ21
DQ19
V
DDQ
V
DDQ
V
SSQ
V
D D
A1
A11
RAS
DQM0
V
SSQ
V
DDQ
V
DDQ
DQ4
DQ2
*2: Top View
Pin Name
CLK
CS
CKE
A
A1
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
A
0
~ A
11
BA
0
~ BA
1
RAS
CAS
WE
DQM
0
~ DQM
3
DQ
0
~
31
V
DD
/V
SS
V
DDQ
/V
SSQ
Substrate(2Layer)
b
z
*1: Bottom View
< Top View
*2
>
#A1 Ball Origin Indicator
K4S283233E-XXXX
SAMSUNG Week
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
1.00
0.27
-
-
-
-
-
0.40
-
Typ
1.10
0.32
9.00
6.40
13.00
11.20
0.80
0.45
-
Max
1.20
0.37
-
-
-
-
-
0.50
0.10
May. 2003
K4S283233E-F(H)E/N/G/C/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
D D
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Mobile-SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T = -25 to 85
°C
for Extended, -25 to 70
°C
for Commercial)
A
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.7
2.7
2.2
-0.3
2.4
-
-10
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+0.3
0.5
-
0.4
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Notes
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
Clock
(V
DD
= 3.0V & 3.3, T
A
= 23
°C,
f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
RAS, CAS, WE, CS, CKE, DQM
0
~ DQM
3
Address(A
0
~ A
11,
BA
0
~ BA
1
)
D Q
0
~ DQ
31
May. 2003
K4S283233E-F(H)E/N/G/C/L/F
DC CHARACTERISTICS
Parameter
Mobile-SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Symbol
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
Test Condition
-60
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
I
CC1
100
Version
-75
85
-1H
85
-1L
80
mA
1
Unit
Note
I
C C 2
P
I
C C 2
PS
I
CC2
N
0.5
0.5
16
mA
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
C C 3
P
I
C C 3
PS
I
CC3
N
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
C C D
= 2CLKs
t
RC
≥
t
R C
(min)
-F(H)E/C
-F(H)N/L
mA
8
5
5
26
mA
Active Standby Current
in power-down mode
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
22
mA
Operating Current
(Burst Mode)
Refresh Current
I
CC4
110
85
80
80
mA
1
I
CC5
180
160
150
130
mA
uA
2
4
5
1500
800
Max 40
500
460
440
Max 85/70
800
650
550
Self Refresh Current
I
CC6
CKE
≤
0.2V
Internal TCSR
4 Banks
-F(H)G/F
2 Banks
1 Bank
°C
3
uA
6
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In Commercial Temp : Max 40
°C/Max
70
°C,
In Extended Temp : Max 40°C/Max 85
°C
4. K4S283233E-F(H)E/C** (85/70°C, Full Banks)
5. K4S283233E-F(H)N/L** (85/70°C, Full Banks)
6. K4S283233E-F(H)G/F**
7. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
May. 2003
K4S283233E-F(H)E/N/G/C/L/F
AC OPERATING TEST CONDITIONS
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
VDDQ
Mobile-SDRAM
(V
DD
= 2.7V ~ 3.6V, T
A
= -25 to 85°C for Extended, -25 to 70
°C
for Commercial)
Value
2.4 / 0.4
0.5 x V
DDQ
tr/tf = 1/1
0.5 x V
DDQ
See Fig. 2
Vtt = 0.5 x VDDQ
Unit
V
V
ns
V
1200
Ω
Output
870Ω
V
OH
(DC) =2.4V, I
O H
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
30pF
Output
Z0 = 50Ω
50Ω
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Symbol
- 60
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
R C
(min)
t
R D L
(min)
t
DAL
(min)
t
C D L
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
Number of valid output data
CAS latency=2
CAS latency=1
-
-
60
64
2
tRDL + tRP
1
1
1
2
1
0
ea
5
12
18
18
42
- 75
15
19
19
45
100
69
84
Version
-1H
19
19
19
50
-1L
19
24
24
60
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
1
2,3
3
2
2
4
1
1
1
1
Unit
Note
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum 2RDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and
precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
May. 2003
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