Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Maxim |
Parts packaging code | DIP |
package instruction | 0.300 INCH, DIP-8 |
Contacts | 8 |
Reach Compliance Code | not_compliant |
series | CMOS/TTL |
Input frequency maximum value (fmax) | 4.16667 MHz |
JESD-30 code | R-PDIP-T8 |
JESD-609 code | e0 |
length | 9.375 mm |
Logic integrated circuit type | SILICON DELAY LINE |
Number of functions | 1 |
Number of taps/steps | 5 |
Number of terminals | 8 |
Maximum operating temperature | 85 °C |
Minimum operating temperature | -40 °C |
Output polarity | TRUE |
Package body material | PLASTIC/EPOXY |
encapsulated code | DIP |
Encapsulate equivalent code | DIP8,.3 |
Package shape | RECTANGULAR |
Package form | IN-LINE |
power supply | 5 V |
Maximum supply current (ICC) | 75 mA |
programmable delay line | NO |
Prop。Delay @ Nom-Sup | 150 ns |
Certification status | Not Qualified |
Maximum seat height | 4.572 mm |
Maximum supply voltage (Vsup) | 5.25 V |
Minimum supply voltage (Vsup) | 4.75 V |
Nominal supply voltage (Vsup) | 5 V |
surface mount | NO |
technology | CMOS |
Temperature level | INDUSTRIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
Total delay nominal (td) | 150 ns |
width | 7.62 mm |