256K x 32 Static RAM
PUMA 68S8000X - 012/015/017/020
Issue 5.1 August 1999
Description
The PUMA68 range of devices provide a high
density surface mount industry standard memory
solution which may accommodate various memory
technologies including SRAM, EEPROM and
Flash. The devices are designed to offer a defined
upgrade path and may be user configured as 8, 16
or 32 bits wide.
The PUMA68S8000X is a 256Kx32 SRAM module
housed in a 68 Jleaded package which complies
with the JEDEC 68 PLCC standard. Access times of
12, 15, 17 and 20ns are available. The 5V device is
available to commercial and industrial temperature
grade.
512Kx32 SRAM PUMA68 devices are available in
the same footprint to offer a defined upgrade path.
Block Diagram
/BS3
/BS2
/CS2
/BS1
/BS0
/CS1
256K x 16
256K x 16
/OE
/WE
D0~15
D16~31
A0~17
Features
• Access times of 12, 15, 17 or 20ns.
• 5V + 10%.
• Commercial and Industrial temperature grades
• 68 J Lead Suface Mount Package.
• JEDEC standard footprint.
• User Configurable as 8 / 16 / 32 bits wide
• Operating Power
(32 Bit) 2.86W (max)
• Low power standby. (TTL) 660mW (max)
(CMOS) 110mW (max)
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
Chip Select
Byte Select
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A17
D0~D31
/CS1~2
/BS0~3
/WE
/OE
NC
V
CC
V
SS
Package Details
PUMA 68 - Plastic 68 ‘J’ Leaded Package
Max. Dimensions - 0.988” x 0.988” x 0.200”
11403 West Bernardo Court, Suite 100, San Diego, CA92127.
TEL (858) 674 2233, Fax No. (858) 674 2230 E-mail:
sales@mosaicsemi.com
Absolute Maximum Ratings
(1)
DC Operating Conditions
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T
P
T
T
STG
(2)
Min
-0.3
to
2.0
-55
to
Max
+7.0
Unit
V
W
+125
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
(2) V
T
can be -2.0V pulse of less than 10ns
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial)
(Industrial)
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
V
CC
+0.3
0.8
70
85
Unit
V
V
V
O
O
C
C
DC Electrical Characteristics
(V
CC
=5V+10%, T
A
=0
O
C to +70
O
C)
Parameter
Input Leakage Current
Output Leakage
Current
Operating Supply
(2)
Current
32 Bit
Address,
/OE,/WE
Symbol Test Condition
I
LI
I
LO
0V < V
IN
< V
CC
/CS1~2=V
IH
, V
I/O
=GND to
V
CC
Min. Cycle,
/CS1~2=V
IL
,V
IL
<V
IN
<V
CC
-
2.1V,/BS0~3=V
IL
Min. Cycle,
,/BS0~3=V
IL
,V
IL
<V
IN
<V
CC
-
2.1V,/CS1=V
IL
or ,/CS2=V
IL
/CS1~2=V
IH
/CS1~2
>
V
CC
-0.2V, 0.2V
<V
IN
<
V
CC
-0.2V
I
OL
=8.0mA
I
OH
=-4.0mA
Min
-4
-4
Typ Max Unit
-
-
4
4
µ
A
µ
A
I
CC1
-
-
520
mA
16 Bit
I
CC2
-
-
310
mA
Standby Supply Current
TTL
CMOS
I
SB1
I
SB2
V
OL
V
OH
-
-
-
2.4
-
-
-
-
120
20
0.4
-
mA
mA
V
V
Output Voltage Low
Output Voltage High
Notes : Typical Values are at V
CC
=5.0V, T
A
=25
O
C and specified loading.
PAGE 3
Issue 5.1 August 1999
Capacitance
(V
CC
= 5.0V+10%, T
A
= 25
O
C)
Parameter
Input Capacitance, (
Address, /OE, /WE)
I/P Capacitance, (other)
I/O Capacitance, (
16 bit mode - worst case)
Note : These Parameters are calculated not measured.
Symbol
C
IN1
C
IN2
C
I/O
Test Condition
V
IN
=0V
V
IN
=0V
V
I/O
=0V
Min
-
Typ Max
-
20
10
Unit
pF
-
-
24
pF
Test Conditions
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
V
CC
= 5V+10%
Output Load
I/O Pin
645Ω
1.76V
100pF
PAGE 4
Issue 5.1 August 1999
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