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Remember to give due consideration to safety when making your circuit designs, with ap-
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flammable material or (iii) prevention against any malfunction or mishap.
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How to Use This Manual
This hardware manual provides detailed information on features in the M16C/28 Group
microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and micro-
computer.
Each register diagram contains bit functions with the following symbols and descriptions.
XXX register
b7
b6
b5
b4
b3
b2
b1
b0
*1
Symbol
XXX
Address
XXX
After reset
00
16
0
Bit symbol
XXX0
Bit name
XXX bit
b1 b0
Function
1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
RW
RW
*2
XXX1
RW
(b2)
Nothing is assigned.
When write, should set to "0". When read, its content is indeterminate.
(b3)
Reserved bit
Should set to "0"
RW
*3
XXX4
XXX bit
Function varies depending on each
operation mode
RW
XXX5
WO
XXX6
0: XXX
1: XXX
RW
XXX7
XXX bit
RO
*1
Blank:Set to "0" or "1" according to your intended use
0:
Set to "0"
1:
Set to "1"
X:
Nothing is assigned
*2
RW:
RO:
WO:
–:
*3
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to "0" for new function
in future plan.
• Reserved bit
Reserved bit. Set the specified value.
• Avoid this setting
The operation at having selected is not guaranteed.
• Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
Read and write
Read only
Write only
Nothing is assigned
Table of Contents
Quick Reference to Pages Classified by Address ......... B-1
1. Overview ............................................................................ 1
1.1 Applications............................................................................................... 1
1.2 Performance Outline ................................................................................. 2
1.3 Block Diagram ............................................................................................4
1.4 Product List ............................................................................................... 6
1.5 Pin Configuration .......................................................................................8
1.6 Pin Description .........................................................................................10
2. Central Processing Unit (CPU)....................................... 12
2.1 Data Registers (R0, R1, R2 and R3) ........................................................12
2.2 Address Registers (A0 and A1)...............................................................12
2.3 Frame Base Register (FB) .......................................................................13
2.4 Interrupt Table Register (INTB) ...............................................................13
2.5 Program Counter (PC) .............................................................................13
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ................13
2.7 Static Base Register (SB) ........................................................................13
2.8 Flag Register (FLG) ..................................................................................13
2.8.1 Carry Flag (C Flag) ................................................................................................. 13
2.8.2 Debug Flag (D Flag) ............................................................................................... 13
2.8.3 Zero Flag (Z Flag) .................................................................................................. 13
2.8.4 Sign Flag (S Flag) ................................................................................................... 13
2.8.5 Register Bank Select Flag (B Flag) ....................................................................... 13
2.8.6 Overflow Flag (O Flag) ........................................................................................... 13
2.8.7 Interrupt Enable Flag (I Flag) ................................................................................ 13
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................ 13
2.8.9 Processor Interrupt Priority Level (IPL) ............................................................... 13
2.8.10 Reserved Area ...................................................................................................... 13
A-1
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