GS8182Q18GD-250T datasheet, PDF

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GS8182Q18GD-250T: DescriptionStandard SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, MO-216CAB-1, BGA-165; Categorystorage storage; File Size450KB，29 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8182Q18GD-250T Overview

Standard SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, MO-216CAB-1, BGA-165

GS8182Q18GD-250T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

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Preliminary

GS8182Q18/36D-250/200/167/133

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +150/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

18Mb

2x2B2

SigmaQuad-II SRAM

133 MHz – 250 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

-250

tKHKH

tKHQV

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.7 ns

0.5 ns

-133

7.5 ns

0.5 ns

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

JEDEC Std. MO-216, Variation CAB-1

Because Separate I/O

2x2B2 RAMs always transfer data in two

packets, A0 is internally set to 0 for the first read or write transfer, and

automatically incremented by 1 for the next transfer. Because the LSB

is tied off internally, the address field of a

2x2B2 RAM is always one

address pin less than the advertised index depth (e.g., the 1M x 18

has a 512K addressable index).

SigmaRAM™ Family Overview

GS8182Q18/36 are built in compliance with the SigmaQuad-II

SRAM pinout standard for Separate I/O synchronous SRAMs. They

are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of

wide, very low voltage HSTL I/O SRAMs designed to operate at the

speeds needed to implement economical high performance

networking systems.

two input register clock inputs, K and K. K and K are independent

single-ended clock inputs, not differential inputs to a single differential

clock input buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and C

clock inputs. C and C are also independent single-ended clock inputs,

not differential inputs. If the C clocks are tied high, the K clocks are

routed internally to fire the output registers instead.

Clocking and Addressing Schemes

2x2B2 SigmaQuad-II SRAM is a synchronous device. It employs

Rev: 1.01a 8/2003

1/29

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8182Q18/36D-250/200/167/133

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.

Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular

in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the

RAM’s bandwidth in half.

A SigmaQuad-II SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM

that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer

protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which

a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad-II SRAMs

support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the

same internal circuits. Differences between the truth tables of the different SigmaQuad-II SRAMs, or any other Separate I/O SRAMs, follow from

differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and

disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application

at hand.

Alternating Read-Write Operations

SigmaQuad-II SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.

Rev: 1.01a 8/2003

5/29

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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