IDT71V124HSA20PHG datasheet, PDF

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IDT71V124HSA20PHG: DescriptionStandard SRAM, 128KX8, 20ns, CMOS, PDSO32, ROHS COMPLIANT, TSOP2-32; Categorystorage storage; File Size116KB，8 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71V124HSA20PHG Overview

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, ROHS COMPLIANT, TSOP2-32

IDT71V124HSA20PHG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSOP2
package instruction	ROHS COMPLIANT, TSOP2-32
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	20 ns
JESD-30 code	R-PDSO-G32
JESD-609 code	e3
length	20.95 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	10.16 mm

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3.3V CMOS Static RAM

1 Meg (128K x 8-Bit)

Center Power &

Ground Pinout

◆

IDT71V124SA/HSA

Features

128K x 8 advanced high-speed CMOS static RAM

JEDEC revolutionary pinout (center power/GND) for

reduced noise

Equal access and cycle times

– Commercial: 10/12/15/20ns

– Industrial: 10/12/15/20ns

One Chip Select plus one Output Enable pin

Inputs and outputs are LVTTL-compatible

Single 3.3V supply

Low power consumption via chip deselect

Available in a 32-pin 300- and 400-mil Plastic SOJ, and

32-pin Type II TSOP packages.

Description

The IDT71V124 is a 1,048,576-bit high-speed static RAM organized

as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability

CMOS technology. This state-of-the-art technology, combined with inno-

vative circuit design techniques, provides a cost-effective solution for high-

speed memory needs. The JEDEC center power/GND pinout reduces

noise generation and improves system performance.

The IDT71V124 has an output enable pin which operates as fast as

5ns, with address access times as fast as 9ns available. All bidirec-

tional inputs and outputs of the IDT71V124 are LVTTL-compatible and

operation is from a single 3.3V supply. Fully static asynchronous

circuitry is used; no clocks or refreshes are required for operation.

◆

Functional Block Diagram

•

ADDRESS

DECODER

•

1,048,576-BIT

MEMORY ARRAY

I/O

- I/O

I/O CONTROL

CONTROL

LOGIC

3873 drw 01

OCTOBER 2008

DSC-3873/09

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