HY57V12820LT-K datasheet, PDF - EEWORLD Datasheet

HY57V12820LT-K: DescriptionSynchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size139KB，12 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V12820LT-K Overview

Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
JESD-609 code	e6
length	22.22 mm
memory density	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	54
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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